The Level 1 SciFi Trigger A Fast Track Trigger implemented with FPGA's

11/4/98


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Table of Contents

The Level 1 SciFi Trigger A Fast Track Trigger implemented with FPGA's

The Fiber Tracker L1 Trigger Group

The Detector

Physics Goals

Tevatron Impact

DØ Tracking

Fiber Tracker

Tracking Trigger

Trigger Schematic

Trigger Architecture

System Overview

SciFi VLPC Cassette

FE Board Signal Flow

FE components: SIFT + SVX

SIFT Threshold

SIFT Gain to SVX

Track Finding

Seamless Tracking

Signal Routing

Track Finding (cont.)

Track Binning

Track Finding (cont.)

FPGA’s

Time to L1 Muon

Trigger Concentrator System

CFT/CPS Geometry

L1 Receiver/Concentrator

L1CFTTM

L2CFTCN

L2CN

Tracks for L2

To L2STT

To L2CFT

Summary

backup slides

List of Terms

The VLPC

L1/L2 Trigger Configuration

Trigger Example

Front End ‘Crates’

 Author: DZERO

Email: stefan@fnal.gov

Home Page: http://d0server1.fnal.gov/www/stefan/Welcome.html

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