Minutes of DFE meeting, June 12, 2001 1. Double Wide Daughter Board assembly Jamieson reported that though Circuit Service had said the first board BGA assembly would be here last Friday, they now say this Friday (June 15). It will take about a day to load the discrete components and test for connectivity. Following successful test, if this happens, we would be in position to cut the order for the full set of DWDB. Fred asked if we knew the FPGA complement for all boards. Levan replied that we do (barring the STT boards) with the possible exception of DFES and CPSS -- but for these in fact we can probably extrapolate fairly well from the needs for other boards and existing partial simulations. We estimate it will be a four week cycle for Circuit Service to place BGAs on all production boards, with testing and discrete placements to follow. The socketed board from Alabama firm has arrived; not yet tested. If satisfactory, Jamieson expects they can do the FPGA placement without difficulty. We will need to decide in a couple of weeks whether to place orders for some/all boards with them, depending on the Circuit Service experience. (recall they cost $100/bd and have 48 hour turnaround.) Fred reported that Sanmina reps were here and saw a DWDB. They claim they can mount FPGAs satisfactorily. We have one working CTOC and one CTQD now. Others in hand require rework. To do this will drain resources. 2. Mixer Stefano and Neal report they have one functional Mixer board. They finished the clock changes last week and think this part is OK. They operate with a set of input vectors generated by spreadsheet and sent to data pump and on to the Mixer. The output is then available to compare with the simulator based on the layout system to see if hardware performs as expected. They do one vector at a time, but have sufficient flexibility that they can test all the connections of a supersector (4 boards) and see the outputs are right -- perhaps in a several day run. They will start now to commission a second board. Tests are needed to verify all the connections, clocks, backplane connections, interboard connections etc. They estimate 2 - 4 weeks for this. Only on completion would one go to make the bare boards for the rest of the system. Imagining 4 weeks for production of boards, 2-4 weeks for test and shakeout, we are looking at 10 weeks to complete. Stefan noted that this is taking us to September, and we will be in a big rush to try to commission during the September shutdown. We asked about trying to speed up the initial tests of the 1st two boards to help shorten the lead time. Fred was pessimistic as this test is crucial to get right. But Fred will discuss with Stefano and Neal to see how to move faster, and to see if extra D0 help could be used. Fred says the documentation of the mixer project is in good shape. The prototype board can be used with an AFE/Mix/DFE combination in D0 to get system experience rather soon. 3. Testing on the platform. We still have not seen evidence of the AFE clock. AFE monitor code was upgraded. The AFE board (RH RevA Bd 9) has 1553 connection and could read the SVXprime. We do plan to remove this board since it is the one that we modified for CPS charge split tests -- as soon as there is an access. AFE bd 4 can be used for platform tests, despite the fact that its download capability is suspect. The tests of the same hardware in DAB3 worked well -- clocks were present. So the real work here is to get a similar operation on the platform, and for this access is needed. Stefan reported that though the VRB controller is not right, we do see all the events that a DFE board sends. The first event is OK, but subsequent events are garbled. 4. Mrinmoy said that the frame swap seen in Examine after sending events through the whole chain is still there and not understood. Such swaps are not apparently present in other systems. Mrinmoy is looking for Scott to confer, and trying to find a program or compiler problem somewhere.