Minutes of DFE meeting, June 5, 2001

Levan Babukhadia, Mrinmoy Bhattacharjee, Fred Borcherding,
Paul Grannis, Satish Desai, Rick Jesik, Yildirim Mutaf,
Jamieson Olsen, Kyle Stevenson

      +-----------------------------------------------------------+
      | Action items:                                             |
      |                                                           |
      | 1.  Need to keep on top of Circuit Service to get         |
      |     the first DWDB delivered and tested.   Arrival        |
      |     of DWDBs is a pacing item, and is not expected        |
      |     to be complete until end of summer.                   |
      |                                                           |
      | 2.  Testing the Mixer board synapse connection integrity  |
      |     needs attention.  We need to identify a person who    |
      |     can devote considerable time to this over the summer. |
      |                                                           |
      | 3.  We need access time to the platform to continue to    |
      |     debug the clock and controls operation of AFE/DFE     |
      |     boards installed there.                               |
      +-----------------------------------------------------------+

1. Platform testing

Fred and Jamieson reported on tests of boards in the platform in 
Stefan's absence.  We are still not getting sensible readouts due
to lack of clock signals.  Attempts to reproduce the problems in the
DAB3 setup failed (things worked!).

The control bits were added to the firmware on the platform AFEs.
We are in need of some time to access and play with the hardware on
the platform to make progress here.

2.  Hardware status

DFEA assembly in PREP continues; no estimate available for completion.

Circuit Service has the order for one DWDB board to install the BGAs.
Johnny Green is keeping on top of the progress.  The current estimate
is still 4 weeks (July 2) for delivery of this board.  On receipt, it
must have discrete components added at PREP (a few hour job).   Tests
will be conducted in DAB3 before committing to the full order of all
DWDB BGA installation.  This is guessed to take another 4 weeks.  Then
there is testing here (4 weeks??).   So all this translates into 
a full system in September if all goes well.

A socketed board from XXX in Alabama is being made and is expected
soon.   If they can do the sockets, we believe they could also do
BGA installation if need be.   This then forms our backup, but will
cost $100 per board (there are about 40 DWDBs in the system, exclusive
of 12 STT boards).   Turnaround at XXX is believed to be 2 days.

We discussed how we can commission all elements of the trigger chain
with the 5 DWDBs that we would expect to have in hand after the
socketed board and Circuit Service board are here.  We believe that
we can test communication and functionality for all parts of CTT/PS
triggers with these, so that we should be in a position to commission
rapidly once the remaining DWDBs are delivered and tested.

3.  Mixer

Fred reported that 2 boards are stuffed and ready to be tested with
the data pump.   The clock distribution system is done, but needs
testing.   We estimate 4 weeks before committing to the full order of
mixer boards (five supersectors of 4 boards each).

Maps for the mixing were prepared by a mix of John Anderson, Jamieson,
Stefano and checked by Fred.    We discussed the plan for full testing
that signals come in and are routed to where they should be.  No clear
mechanism for this exists.   Ideally, we will want to test a system of
the four boards in a supersector together.  We discussed a variant in
which multiple signals from the data pump could be fed to the mixer,
and various patterns cycled through to test a sector of the inputs.
We also noted that a simpler software scheme where each individual
channel is fired and found after the mixer.  Both, particularly the
latter scheme, will be labor intensive requiring many changes of
connections.   We believe that the testing will be crucial however,
since misunderstanding the map will translate into inefficiencies for
CTT/CPS tracking.   We need to find a person who can devote the summer
to developing this test process under Jamieson's supervision.
This can begin now with a one mixer board version of the testing.

4.  Firmware

Levan reported that all elements for testing the occupancy trigger are
now in hand, though it was not clear that the synch code had actually
been incorporated into the CTOC firmware.   Though there will be fixes
and upgrades as we go through commissioning, we think we are in good
position to begin.

5.  Examine

Mrinmoy reported on the bare-bones Examine project.   The issue at
hand is finding the location of all the bytes, and understanding the
complex pattern of byte swaps and maps.   Using test vectors created
by Yildirim on the DAB3 setup reading into the L3 nodes and on to
Examine, considerable progress has been made in understanding the
mapping.  All bytes are seen in the output.  One non-understood byte
swap is seen that needs to be understood.  The VRB header information
is not fully understood.