L1 CTT/PS meeting minutes May 8, 2001 -------------------------- Present: Levan Babukadia, Mrinmoy Bhattacharjee, Jerry Blazey, Fred Borcherding, Satish Desai, Paul Grannis, Stefan Grunendahl, Yildirim Mutaf, Rick Jesik, Manuel Martin, ... 1. Sanmina is slow in getting the stuffing going. No AFE before end of May. Priority for next week is work on platform. We will put about 8 AFE RevA boards in to power up and check out. 2 will be left in. Some green wires are to be installed to allow syncronization and to give AFE timing signals out. 2. Fred B. reviewed a slide from Jamieson. 20 DFEA boards are fully ready to install, with modified transition card to avoid the bent pins. Others are in test by us; PREP is working on the rest. We will populate one of 2 DFEA crates in platform center (PC). LVDS cables will go to CTOC (Platform west=PW) and Muon. We have one CTOC and one CTQD board available. BEST and Retronix have not succeeded in mounting BGA's. We are waiting for Circuit Service to come back with test results on a bare board and BGA mechanical assembly. They have a uniform temperature oven, not spot heating and were recommended by Nick at Aldec. We decided that the CTOC and CTQD would remain in DAB3. The DFE crates are all present and ORC is available. All FPGAs for CTT/PSax/FPS are ordered and on hand. 7 of 10 DFEC boards are ready. We were uncertain of the status of DFEC code for the DWDB. It was pointed out that we don't need the firmware assembler PC software to run in DAB3 with the special VRB to the Level 3/online. The suggested plan was to install one DFEA in the CTOC crate on PW, with a GLink output that we could if desired use to collect data from one DFEA and ship to L3 on the standard experiment path if we can. Some special firmware in the CTOC surrogate would be needed, and we thought not to do more than pass patterns with this setup in the foreseeable future. Solving the DFEC issues and getting remaining DFEA code for occupancy triggers seemed higher priority, and these will occur in DAB3. Thus the plan for the platform at end of shutdown would be : +------+ +--------+ +-----+ | DFEA |-----| DFEA |=========| L3 | --- LVDS +------+-* | used | +-----+ === Glink | |as CTOC | +-----+ ... FCSA = ATMC | +--------+........ |MuTM | | +-----+ +------+ |MU L1 | +------+ We will set up AFE in a crate upstairs to send patterns to DFEA and on to the working CTOC and CTQD operating as CTTT, for testing the pattern transfer to L3 and system test. +-----------------------------------------------------------+ | Questions for Jamieson: | | | | What is the status of the PC code for DFEC? | | is Nick finishing this? what is the schedule? | | what load on Jamieson? What alternatives if | | Nick is not available? Paul Padley engineer? | | | | What is status of firmware in DFEC for DWDB? | | schedule, load on Jamieson? | | | | What is status of BEST return, Retronix return | | Circuit Service attempt to load BGA? What load | | on Jamieson? What are we doing to develop alternate | | vendors? Any others from Nick as possibles? | | | | What fraction of Jamieson's time is spent now serving | | platform needs? What alternatives? are we getting | | good use of the 40% of Shoua Moua? More help of this | | sort needed? | | | | What is needed to bring the test crate in DAB3 | | up to full functionality for testing several boards | | with data pump input? | +-----------------------------------------------------------+ 3. Levan reviewed firmware. We should have a hit occupancy trigger by end of May; need to check downloads, use of DFEC, link test with multiple DFEA boards, use of L1 - L3 examines. L1FPS all done (implement synchronization and L3 sender, but the module exists) L1CTT/CPSax full functionality. need the final DFEA cluster code (end June) L2CTT/PSax: again, need final DFEA firmware, CTQD firmware (we have only functional design at present) (end July-Aug.?) L2CPSax: decide on FPGA needs. We heard that the cluster algorithm uses about 10% so do not anticipate problem in fitting in the syncronization module and L3 sender. +-------------------------------+ |Decide on FPGA here in 2 weeks | +-------------------------------+ Levan followed with more detail on issues remaining for each piece of firmware. We discussed without resolution, the status of the crate test stand in DAB3 for testing more than one board, data pump input. for simulated event data. See: http://d0server1.fnal.gov/users/levan/upgrade/L1General/L1CTTPS_Mtg_050801.ppt 4. Mrinmoy reviewed the online examine for testing generic L1 (L2) boards. The package L1trk_examine of Mrinmoy, Yildirim, Zhong Min is in CVS. He noted that examines do not see all events -- only a sampling. There is capability to create templates of frames from ALDEC simulations that can be loaded into Examine to compare with the input from L3. Standard unpacking routines are used. We have exercised this system on fake patterns. We have defined byte patterns that can be loaded at the DFEx so that each byte in the final Examine buffer is unique and locatable. There are so many odd byte swaps along the way in Glink, VRB, VBD, software systems that we are not confident to figure out the ordering of bytes with rational thought. We will ship the patterns and figure out the pattern from the identifiers of the bytes. Note that the plan is to unscramble Examine formats and offline formats of trigger frames to L3 separately (not in common, in say the L3 node.)