Minutes of the AFE Meeting, June 5 ----------------------------------- George Ginther, Marvin Johnson, Fred Borcherding, Jon Kotcher, Paul Rubinov, barn wren, Daniel Mihalcea, Rick Jesik, Alan Bross, John Womersley, Bruce Hoeneisen, Paul Grannis ... 1. Sanmina progress Marvin reported on John Anderson's view of Sanmina assembly progress. At the time of the meeting, 45 back sides of cards were assembled, and they were going very well. They expected the RH boards to be done around June 6. The LH boards would be stuffed when RH boards are finished (next week). Marvin expected the yields to be high. note added: John A.s mail (enclosed below) of June 7 indicates real problems in placing the MCMs, due to non-flatness. Solutions are being sought, but we may have to develop alternatives to Sanmina. SiDet can work on rework of AFE boards; can fix MCMs on a board, or remove MCMs. Some discussion ensued on the necessary burn-in requirements. SMT used a 24 hour burn-in. This needs to be defined. 2. Marvin and Paul R. reported late news that the 1553 interface cards which have not been working well have been found to have a wrong inductor value on them. This mistake seems to have propagated from one board type to another in D0. The old Run I boards (with correct value inductors) worked much better. The AFE board suffers from the same problem. AFE boards may have to be retrofitted to give the appropriate value inductor. We are looking to find the parts. 3. Daniel M. reported on the SiDet test facility. one test stand is working (Stages 3 and 4 of testing) and the second is nearly ready. Software is nearly final and training is starting. The Stage 1 and 2 facilities are OK. 4. Rick J. summarized the DAB3 test status. The test stand is 'about working' (has a last software bug that Mike Matulik is working on). They are starting to do dry test runs this week. There are five students to help with Visual Basic code and offline software. Noise in the test setup is still larger than we would like; there was discussion of building a Faraday cage --thought to be difficult to achieve. Perhaps testing on the Lab 3 setup would aid in noise suppression? 5. Infrastructure on the platform is thought to be in place for AFE installation. There are cables, power supplies, 16 sequencers, so the last piece is the AFEs themselves. There are some remaining firmware fixes for AFE that are not thought to be major issues to complete. We would hope to have half to two thirds of the AFE boards by July to install, with the remainder to go more slowly with rework needed. 6. The board that was modified to look at input charge drains for CPS is now on the platform (where it cannot presently be read). We need to measure the charge response vs. input capacitance, and decided to remove this board at next access to be taken to Lab 3. 7. Marvin summarized the choices we have for new SIFT/MCM for 132 ns operation and Run 2b. His powerpoint slides are referenced under section 8 of the afe page. The three choices outlined are: a) replace only SIFT (remove MCM and rework) MCM removal yields are a problem. We don't solve the SVX DNL or pickup problems. This would be a FNAL manpower intensive solution, that has high risk (we did not solve these problems for Run 2a!) It also leaves us with a board for which it is very difficult to do diagnostics due the low charge everywhere. b) replace the SIFT and add an 18 channel pipeline before the existing SVX chip. this would enable the SVX to access data always in the same point in the clock cycle and allow clearing SVX before charge transfer and eliminates SVX pickup. Monitoring of charge out of SIFT in the pipeline would be improved, and the SVX would be a 1-deep digitizer only. c) build a MCM replacement with extensive FPGA control and clock, FADC digitizing following the SIFT circuit. The new daughterboard would have the same footprint as an MCM and would be thinner, so would be replacement on AFE for the MCM. The new daughterboard would have effective 10 bit range, so could serve CFT and preshower. The board would use the 0.25 micron technology from TSMC. Submission of prototype chips could be done with BTEV (or other projects) to get us to the minimum order size of 10 wafers. Risk for this option was thought to be the lowest of all, as many of the design elements are already done, and simulation tools are good. The 10 bit range is thought to be enough for preshowers; dual threshold would be nice, but is actually more needed for Run 2a where low pT physics plays a stronger role. Total cost of option c), with 50% contingency, would be ~$300K plus TSMC costs. This is perhaps $100K more than the SIFT replacement. The consensus of the meeting was to go with the FADC/FPGA daughterboard, and Jon Kotcher subsequently affirmed this as our decision and has discussed with the Lab. The decision mentioned a baseline in which there was one discriminator threshold for preshowers. Milestones remain to be laid out for reviews of design, functionality and production. ----------------------------------------------------------------- From: SMTP%"janderson@fnal.gov" 7-JUN-2001 17:00:58.47 To: GRANNIS CC: Subj: AFE assembly at Sanmina Gentlemen: Sanmina has informed us that there are significant and difficult problems related to the assembly of the MCMs onto the boards. While assembly of all the other components appears to be working smoothly, a number of mechanical issues conspire to make the MCMs very difficult. Sanmina is trying to assemble the boards by screening solderpaste onto them, using pick-n-place machines to put all parts except the MCMs down and then hand-placing the MCMs. This is because the MCMs are too large and too heavy for most pick-n-place machinery. Hand placement is not an issue of significance. It is fairly easy to hand-place the MCMs with sufficient accuracy. However, once placed, the MCMs don't sit flat on the board. Even with weights placed on each MCM sufficient non-planarity of the leads results in numerous open joints after reflow. In addition, the MCMs themselves don't settle like other parts, requiring that the four corner pins be hand-tacked with a soldering iron prior to entering the reflow oven. Each MCM is showing up with multiple open joints. Sanmina estimates that it takes 2 hours per board to perform the necessary rework to get all pins soldered. Their cost for rework is $50 per hour, which means an extra $14,600 if we ask them to do it all. They have suggested that a heavier paste application may reduce the number of opens on the board, with the associated risk of possible shorts on some of the smaller components. I have authorized them to build a second solderpaste application screen at a cost of approximately $450 to test this idea. None the less, I still expect there to be opens which will require rework. The process engineer at Sanmina has tried all sorts of tricks with weights and clamps to try and eliminate the opens, but to no avail. The MCMs are just too mechanically "wild". A further issue is that the pad size on the board for the MCM pins is too small for the "foot" of the lead itself. While electrically and mechanically good solder contacts can be obtained after rework, these contacts don't cut it under the inspection standard specified in the contract. The only viable compromise I see here is to send them a written agreement in which we agree to release them from conformity to the inspection standard for the 8 MCMs, and only the 8 MCMs, on each board. This would insure the quality level everywhere else but allow them to build and ship to us in a reasonable time frame. We would then accept the responsibility to perform the resoldering of MCM leads prior to testing the boards. I've already asked Fred to contact Marcel and Bob Jones regarding available labor and he reports that both have responded favorably. Sanmina will be reporting the results of the heavier solderpaste to me tomorrow and we will proceed from there. John