Some D0 (Upgrade) Notes

Design of a Hardware Testing System for the D Zero Detector html file

Published in "IEEE TRANSACTIONS ON NUCLEAR SCIENCE" August 1993, Vol. 40, Number 4, PART II OF TWO PARTS, ISSN 0018-9499, pp. 1282-1285 Angstadt, Johnson, Martin, Matulik, Utes
(Older) P.C. DOS based Bit3 based Detector Hardware test software. Has some diagrams of how a model 403/406 Bit3 boardset works. May provide additional background on the more current D0 Note 2589.

D0 note 2589 Postscript file (405,676 bytes)D0 note 2589 html file

Using Modern Software Tools to Design, Simulate and Test a Level 1 Trigger Sub-System for the DZero Detector (presented at 1995 IEEE Conference on Real Time Computer Applications in Nuclear Particle and Plasma Physics (RT-95), Michigan State Univ. May 23-26, 1995) Angstadt, Borcherding, Johnson, Moreira
Example of VME access directly into and out of an Microsoft Excel spreadsheet running on a Microsoft 3.x or Win-95 Intel P.C. via a Bit3 (models 403 or 406) with Visual Basic for Applications and a DLL written in "C". Performance spechs are given. It's strength is relative ease of use, flexibility and rapid prototyping. This technique is used by most electronics engineers at D0 to help develop our next VME based data acquisition system. It has also been used as a small DAQ to collect VME data and write it to a file on the P.C..
Installation instructions for the Bit3 drivers for NT and/or Win2k. (note 2589)

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(Some) History/updates/addendium to the above note. (note 2589)

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Converting spreadsheets to work with different Bit3 models and/or different Operating Systems (Win 9x or NT) in about 5 minutes. (note 2589)

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D0 note 3058 Postscript file (81,995 bytes) D0 note 3058 html file

D Zero Central Hardware Trigger Preliminary Implementation Studies of the "Base Line Design" Angstadt, Borcherding
This is a brief study of how many Track Finding equations can be fit into the Altera 10K50 and 10K100 FPGA's (Field Programmable Gate Arrays)

D0 note 3168 Postscript file (666,422 bytes) D0 note 3168 html file

D Zero Central Hardware Trigger Preliminary Implementation Studies of Weighted Averaging of 'Clusters'" Angstadt, Johnson
This is another brief Altera fitting study of Mathmatical (DSP) routines including some timing simulations into FPGA's.
Correction: the weighted average number of bits used was too small in D0 note 3168. This study is superseded by D0 Note 3209 (especially pages 5,6 and 9): D0 note 3209

Postscript file (without figures). (Apologies 1/30/2001 R. Angstadt)

D0 Note 3479 html file

includes VME-Metro traces of an upgraded VBD working with two VRB's! Address and performance discussion as well as programming sequences.

"HV User's Manual Version 2.08 for an IBM AT or Clone" html file

This software documentation replaces, and supercedes the original one by M.J. Yang which was D0 note #1175 Version 1.0. This is the P.C. based "HV" program that supports up to four VME crates using Vertical Interconnect hardware. The Last 3 pages include a description of how to set up the hardware jumpers on the HV boards.

"'HVD' (High Voltage Display) Program for the PC" html file

This is basically D0 note #1257 which is the documentation to go with the stand alone "HVD" single VME crate version that has been released into the commercial domain via Bira.