DØ Level 1 CFT/CPS/FPS Trigger

Old Stuff

System Overview diagram

News:

2002-1-24: various shutdowns/accesses later:

  • the last missing modules (4*FPSS,2*DFEF,12*STOV/STSX) are at FNAL, being stuffed and then tested. Estimated time to completion: one month.
  • the south side modules have been installed and cabled (Abid et al.), except for the four FPSS in PC20-2-10/11/12/13, and two DFEF in PC19-2-14/15.
  • firmware chain tests will hopefully soon make progress: fake track patterns have already been sent from the AFE through the Mixer system to a datapump at the CTS (Combined Test Stand on DAB3-west) (Paul, Makoto).
  • test patterns have been sent from a standalone G-link sender at the CTS to the STT L2 receiver on the 2nd floor of the MCH (Stefan, Georg).
  • Steve Linn is working on a combined SVX/CTQD sender for STT testing.
2001-11-26: after the weekend shutdown extension and the Monday noon access:
  • AFE-Mixer and Mixer-DFEA problems have been mostly eliminated, at least as far as clock and synchronization flag recognition goes. The full test pattern recognition for the AFE to Mixer link still shows some instability, and needs further investigation. Two Mixer boards were replaced in the Monday noon access. Stefano had resoldered and tested three spare boards. Platform replacement had been scheduled for Sunday, and did not happen due to end of access. Problems seem to be due to bad solder joints, similar to AFE problems (Surya no-wash solder ?).
  • CPS axial: Links to the Mixer were redistributed such that each supersector gets a valid clock from an existing AFE board.
  • CPS/FPS south: all L3 output links were plugged in, except for DFES #4, which has no transition module yet. Each of the three DFES boards in PC19 crate 2 slot 2 to 4 has a CPS link from cryoslot 18 (populated) into link 2 (the master clock link). So, if there were firmware, it could be tested by reading out to L2 and L3.
  • PC19-2 has a CF and is powered up, PC20-2 does not, has no modules, and is powered down.
  • West Side: Carsten was working on the CTTT-MTM-TFW link.

2001-11-21: After the shutdown (first part; access to continue on Friday, 2001-11-23):
We pretty much got done with everything. There's some Mixer-to-DFEA debugging that remains for Friday, plus one AFE-to-Mixer cable replacement, plus a few missing AFE boards. The DFEF input cabling will have to wait for boards, the four DFES's that made it in will get their clocks on Friday.

2001-11-17: Task list for last week of shutdown.
Brief summary:
  • Cables and modules in place for CFT/CPS axial.
  • Finishing work on infrastructure for remote operation (download tests).
  • Remote MTM power supply control is working.
  • link tests (complete cabling checks) have been run for Mixer-to-DFEA (15/320 need further investigation) and for part of AFE-to-Mixer (7/230 need checking).
  • Preparing for FPS and CPS installation and cabling, if/when boards become available. Up to five boards might go in before the end of the shutdown.

2001-8-27:
2001-7-19: AFE(rev1a)-DFEA link successfully tested on DAB3n test stand.
2001-7-14: Clock signals are getting to the central platform DFEAs. The AFE output format is not yet matching DFEA expectations; a Sequencer code modification is required. The CTOC code is being ported to the single-wide daughtercard; this is also needed to complete the 2-layer occupancy trigger chain.
2001-6-28: After yesterday's access, 4 DFECs (PC03 top and bottom, PW03 top and bottom) have new 1553 transformers. Little luck getting consistent 1553 communication going. Damage to 1553 cables at exit from MCH 3 discovered (Shua, Eric K.) and repaired. 1553 bus map updated, to make cable labels consistent with bus 2 cable exchange from last Thursday's access. Double wide board from Circuit Service passed JTAG scan => CTOC production started !
2001-6-15: Some progress has been made towards testing the DFE - AFE connection on DAB 3. One AFE remains on the platform, with the new 1553 transformer. The 1553 bus assignments are again as documented.
2001-6-5: Two AFE boards installed (incl. some last-minute firmware modifications). DFE system cabled for (two layer) hit count trigger. Several problems remain after the end of the four-week access:
  • AFE LVDS clock conundrum (53 MHz for DFE system missing).
  • DFE - VRB G-link protocol (begin-of-record not properly recognized after first event).
The download to the platform and the universal link-test (forwarding) firmware still have to be tested. Some 1553 bus assignments have been temporarily changed.

Estimated timetable for completion of system:

  • end of June: install remainder of DFEA system (second crate).
  • end of July: install double-wide boards (CTOC,CTQD,CTTT etc.) on west platform.
  • July/August: install AFEs.
  • September: install Mixer Box, and cable MB - DFEA connections.

2001-5-22: All connections and modules for the (two-stage) hit-count trigger are in place. DFE crates need to be modified again (power lead connections). DFE PW03-2 readout test has not yet succeeded. Side note: Paul Rubinov and Mike Matulik did calibrate one right handed AFE, which is now installed on the platform, and does feed the two DFEAs in PC03-2.
2001-5-11: DFE readout via L3 working. DAB 3 test crate data seen in standard D0 DAQ (via G-link to VRB in MCH 322-2). Slight modification to 1553 map. All DFE crates modified. MTM production power supply has replaced the prototype in PW02.
2001-5-9: 5 of 7 DFE crates have been modified (transition module alignment). PC south is being worked on. 1553 map updated. Yesterdays commissioning meeting seemed to favour the two-board approach to the hit-count trigger (almost-standard DFEA in PC03-2 with standard LVDS link to non-standard DFEA-as-CTOC in PW03-2, with standard links to MTM and L3). It's about the same amount of not-yet-existing firmware as the single board approach outlined below. Readout crate MCH322-2 had it's power supply fixed, and is still almost working, but now for other reasons...
2001-5-4: 1553 file download confirmed: except for byte swap, everything's fine!
Modified plan for hit count trigger (due to limited double-wide availability): map two AFEs on cassette 34 or 35 to one DFEA in PC03-2; fit that DFEA with both a G-link (L3 R/O) and an AMCC (MTM/ L1 framework) sender. That way we test both paths (DAQ readout and Trigger), and we can (mis)use some of our trigger bits to monitor the card. Only one DFEx card is involved, but we need to pull a few additional cables between PC03 and PW03.
2001-5-3: Platform crates are in process of being retrofitted for better transition card alignment; west platform done. 26 DFEAs tested and ready to install. No word yet on temperature profiling of double wide boards. Download from online file system through 1553 to flash memory tested (but not the readback, so we don't know yet whether we got all the bits into the right places....). Readout crate MCH322-2 has been populated and downloaded, but integration into the DAQ readout awaits fixing of a power supply problem.
2001-4-17: DFEC + DFEx installation in PW03-2 failed (with backplane pin bent by transition module); 1553 communication path to DFECs on west platform tested. 1553 triggering of transfer from DFEC flash memory to DFEx FPGAs successfully (re)tested in FCH3 test crate. ORC in hand since March.
2001-3-1: Crates, power supplies and cables are in place; power supplies on south central and west were tested; no ORC yet. Cables have been prepared for fast installation of occupancy trigger in super sector 2 ( Target date for operation: April 16, 2001). No modules installed yet.

slides:

SciFi L1 status report 26-April-2001
Trigger Meeting (and Commissioning Meeting 2001-5-11).

Sub-Projects and their Status (as of 2001-11-26):