September 24th 2002 CFT Trigger Commissioning Meeting


Index

Hardware

Sequencers, global trigger timing change, Phase V move

DFE_ware, AFE control

CTT integration

L2

Readout, Examine

Discriminator Studies

hardware (Jamieson)

Transition board rebuild (longterm G-link fix): Boards are being manufactured and will be back at the Lab later this week. We should have a stuffed board very soon.

The strange behaviour seen from the CTTT on the platform could be related to an SDAQ run going on at the same time. [We know that an SDAQ run will at its very end set the Sequencer controller into a state unfit for CTT operation.]

The CTOC - CTTT connections have been verified.

STOV - STSX cabling: the same three cables already inspected earlier are still showing up as missing; we will replace the cables during the next suitable access.

PC19 controller problem: no further insight. [The DFEC showed symptoms similar to those of a controller without compact flash memory, but was fixed by a simple reset during an access.] back to index

Sequencers, global trigger timing change, Phase V move (Fred)

Sequencer controllers with new firmware are running ok; the system is ready for the global timing change. There are still several untested features in the new AFE firmware; when the firmware is ready, we will most probably try it in one super sector.

The 'Phase V' AFE test stand move to the area next to the CTS is not imminent; the CTS will however soon gain 1-2 feet on each side of the racks, for accessibility, back to index

dfe_ware, AFE control (Yurii, Makoto)

An online database communication problem shows up occasionally, and is being dealt with by implementing automatic connection retrials.

CTOC monitoring is being implemented.

AFE 30L has been replaced, and the LVDS problem is solved. AFE 46 L&R: the AFEs themselves were swapped, the personality has been verified; next stop: grey cable swap at the AFE backplane (access).

back to index

CTT integration (Levan, Ricardo)

CTOC on the platform: 4 CTOCs seem to properly react to the absence of L1 accepts, the other four do not. A problem was identified with the version of the L3 sender loaded to the platform CTOCs.

Work at the CTS is underway to debug the AFE to CTTT chain, with emphasis on CTOC control bit monitoring and CTOC L3 output.

Levan commented on the strategy to deal with the DFE system pipeline depth issue. The first step is to change from the 32 event times 8 frames pipeline to a 36 event 7 frames pipeline, along with the necessary changes in the L3 sender (Satish).

(Muon) debug cables: cable 48 is currently hooked up to one of the DFEA sector 1 outputs (either 'valid track' or 'transmit enable'); during the next suitable access the other two cables will be connected, one to the second DFEA signal and the other to the input signal from the L1CTT MTM.

back to index

L2 (Steve)

L2STT support continues, with test senders (some free running, most L1 accept synchronized) currently in all DFES and STSX boards.

One 'event-like object' was observed from Theij's production code in a FIC, but no further study was done.

Qichun's DFES code is currently not loaded; tests should be planned once the L2 consumer has been identified.

back to index

Readout, Examine (Stefan, Michael, Kyle)

Crate x13 is still in the readout. Shifter education has to be improved. Comics download scripts for crate x13 and crate 9 (CTS) are making progress.

Michael is still studying histogram reset (not 'comparison', as written last week) solutions in different examines, and hasn't found anything suitable so far. The examine currently needs to be stopped and restarted to reset the histograms.

Histogram comparison can be done right now offline by running the examine twice over the same data (obtained e.g. from SAM) with different input options, each time writing out a root tree, and then overlaying the histograms in a root session. Kyle will document the RCP switch locations for selection of input data (SVX trigsim, VSVX trigsim, crate x13 data).

back to index

Discriminator Studies (Yurii & Yuri)

Yurii and George gave some background on the (planned) discriminator studies: the first goal is to verify the mapping. Once the mapping is understood, VSVX data will be checked against SVX data.

back to index

 

Last modified September 25th, 2002, by SG.
Please send questions or comments to Stefan Grünendahl (Stefan@fnal.gov).