October 15th 2002 CFT Trigger Commissioning MeetingIndexHardwareSequencers, CTS etc.DFE_ware, link testsL1CTTReadout, ExaminesL2CTThardware (Jamieson, Steve)The 3.3 V from the newly installed DFEA power supply for PC03-3 was trimmed up a bit during the access. The initialization failures were due to the dfe_ware code (1553 slowdown, which started about a month ago), though, and not the hardware.Nine of the new transition boards are at SiDet. An upper limit on the error rate was obtained a while ago; 18 errors were counted over 48 hours; some or all of these might be glitches in the counting setup, and not in the G-link connection itself. We plan to install one new transition board on the platform (CTOC in slot 9 ?) in the next access. Two transition boards in the STOV/STSX system were replaced during the last access. CPSS 2 has one bad G-link, and indicates L1_accept always on. The G-link should be swapped,
and the L1_accept investigated by reinitializing the board to see whether this is firmware or
hardware related. If necessary the board should be replaced by a spare.
back to index Sequencers, CTS etc.The CTS reorganization is almost done.Fred thinks the AFE 46L/R problem might not affect the trigger functionality, only the monitoring, since it manifests itself only during readout, when triggers are not produced anyway. Still, it precludes diagnosing real problems in this AFE/Mixer area. John Anderson is implementing more clock and control diagnostics
on the AFEs.
back to index DFEWare, link testsThe initialization sequence was changed, to include waiting for 1553 delays.Yurii is planning to do more STOV/STSX tests, now that two transition boards were replaced during an access. dfe_ware now logs unstable L1_accept and sync bits to a file. L1CTTL1CTT tests yield interesting and puzzling results. A single Trigger sector chain can be made to produce stable (albeit somewhat late) signals at our Muon Trigger Manager, and stable AND/OR term rates. Many ways were discovered to spoil this result (enabling additional trigger sectors, enabling L1_accept control bits, etc.) A debate on the merits of using both 'sync gap' and 'first crossing' in the firmware ensued.Readout, Examines, Trigger SimulatorCTOC readout: The VRB header dump labeling in the Unpacker was updated. There was no byte/word swapping error in the VRB header unpacking.Kyle thinks the Unpacker lacks an important bit of functionality, since there seems to be additional byte-swapping for the DFEA output routed through the CTOC. (Note: Later it was discovered that the unpacker does all it should do, and that the L3 sender has a somewhat unorthodox (to some people) byte-chopping and padding convention. Once implemented in the examine, the data were found to agree perfectly with expectations! As a side effect, Vivek (trigger simulator) was sent into a state of alarm.) L2Firmware status: CTOC L2 CFT code is done (Carsten), and could be tested. Negative interference with the L1 - L3 sender (Ricardo) is currently avoided by disabling L3 sending from the L2 code altogether. This code could thus be tested, and downloaded to the platform, so that L2CFT tests can start.Carsten is now working on the CTOC L2 CPS code (or would be, if he weren't stuck at Octoberfest in Germany). DFEA L2 is running in the test bench right now, and should be ready for platform debugging sometime next week. STT support: test vectors for the STT could originate from many sources. Not all of them will be implemented, at least not in the foreseeable future.
Last modified October 17th, 2002, by SG. |