July 23rd 2002 CFT Trigger Commissioning Meeting

 


Firmware:

DFES: Qichun is at FNAL this week. He has tested his firmware with the Datapump (DP-DFES-DP) and with the AFE (AFE-DFES-DP) and found it working ok. He is now waiting for an opportunity to test it via G-link with a real L2 or L3 receiver.
L2 CTOC,STOV,STOX: The problem Carsten and Nick had been working on evaporated after resynthesizing the VFHDL.


More AFE personality codes:

Makoto has discussed the CPS axial personality code and the accompanying downloads for other chips with John Anderson. The mapping code exists; John is working on special clockgen and vsvxmux files.
CPS stereo (needed for real DFES input): mapping does not yet exist. The clockgen etc. files will be 'normal' (i.e. same as for CFT).


Sequencer status:

On Monday Fred corrected the 264 ns firmware loaded into the crate x52 Sequencers (CPS).
His plan still is to study the basic functionality with crate 52, then to update crate 50 (next week), and then to study SIFT integration timing etc. with crate 50.
During discussion it emerged that there is no reason to delay studies of realistic AFE discriminator thresholds. These studies should not wait for the crate 50 update, but instead start as soon as possible.


Mixer firmware:

Stefano has finished his work on extended diagnostic firmware. He will install it during the next suitable access.

 

Linktest: 

Makoto and Yuri have integrated all AFE-Mixer diagnostics into DFE_ware. Mixer-DFEA is next. Makoto is working on DFEA-CTOC diagnostics.



DFE_ware:

Yuri included a few more checks into the file downloading process. The errors experienced when transferring files to PW03-3 seem gone for good.

 

Readout:   

The CTOC-L3 problem has been solved at the test stand. It seems there are simply too many PLLs in the clock path. The solution involves disabling the motherboard and transition board PLLs on some of the DFEx. This requires one 'green wire' per board. (The G-link PLL modifications mentioned last Friday were not sufficient with more than 2 DFEx-type boards (4 PLLs) in the chain.)
The best way to implement this on the platform, hopefully without ripping everything apart, will be discussed once Jamieson gets back.
At the test stand we are now restarting CTOC L3 studies.


Examine:   

The examine is running (in SVX data - Trigsim mode) online at the CFT station in the control room.