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D0 Note xxxx
Design and Test of the SIFT Chip
University of California, Davis
Fred Borcherding, Marvin Johnson, Juan Lizarazo
A front-end circuit has been developed for the D0 upgrade for reading out visible light photon counters (VLPC’s) associated with the fiber tracker and the preshower detectors. This custom chip, called SIFT, will be used to collect low-level charge signals from the VLPC’s, provide discriminated signals to the L1 trigger system and inject regenerated charge signals into an SVX-II based readout system. The chip R&D is now complete. In this note we present all the measurements that are relevant to the operations of the SIFT.
The SIFT chip was initially designed as a trigger "pick-off" chip for the fiber tracker. Hence, the design parameters reflect the requirements of response to minimum ionizing particles (MIP’s) traversing scintillating fibers. The preshower detectors, however, have vastly different signal properties. We have developed a charge division technique in order to increase the effective dynamic range and resolution of the SIFT and adapt it for reading out the preshower detectors. These studies will be reported in another note.
II. Circuit Design & Functionality
The SIFT chip consists of 20 identical channels, of which 18 will be active and 2 are intended to be guard channels. Figure 1 shows a functional overview of one channel of the SIFT chip. The front-end is an inverting charged sensitive preamplifier with a switched capacitor Cfb (185 fF) in the feedback loop. The output of the preamp is fed into a buffer source follower that drives ac-coupled discriminator and charge driver circuits. The function of the charge driver circuit is somewhat complicated because it has to regenerate a charge impulse and feed it to the SVX in a dc-coupled mode. Hence, the dc bias level of the input of the SVX chip has to be offset by the SIFT. The problem becomes more challenging because there is a 20-30 mV variation from channel to channel in this bias level. In order to minimize spurious charge injection due to this variation, the output capacitance of the SIFT has to be small (100 fF) and well controlled.
The circuits used in the preamp and the buffer amplifier are shown in Figure 2. In order to reduce noise in the front-end, a very wide input transistor (with high transconductance) is used. The speed of the integrating circuit is enhanced by the use of a tree of biasing transistors, which step down the stray capacitance. However, during reset the standing current in the preamp is disturbed and by itself the circuit takes a long time to restore this current to its operating value. In order to speed up this recovery after the feedback capacitor has been reset, an internal pulse, PHDR, is generated across the capacitor C2 (125 fF) capacitor. The charge induced by this pulse at the preamp output node restores the voltage to its operating point. . An external voltage (VDR) controls the height of this pulse. This procedure allows us to minimize the duration of the reset pulse PRST; we have successfully operated the chip with a reset pulse width of only 5 ns but recommend a 10 ns pulse for normal operation.
Figure 1.: A simplified schematic diagram of one channel of the SIFT chip. The blocks consisting of the preamplifier, the discriminator and the charge transfer circuit are shown. The three controlling voltages, V_DR, VCLMP and VREF are highlighted.
discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8. An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator. When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit". When the S/H pulse is applied, this transition is driven off-chip via a series of inverters.
The TH_SEL switch is used to increase the value of C9 by a factor of 5, thus providing a larger range of threshold settings.
Figure 2: The transistor level circuit diagram of the preamplifier. The voltage V_DR is asserted via an internally generated pulse (not shown) following preamp reset.
The discriminator circuit is shown in Figure 3. It operates by setting the bias of the input node at a voltage determined by another internally generated pulse, THSET, which gets divided between the capacitors C9 and C8. An external voltage (VTH) controls the height of this pulse. The difference between the turn-on voltage of the input transistor and the voltage set at the input node determines the effective threshold voltage of the discriminator. When the output of the preamp is large enough to overcome this difference the discriminator input node switches "on" signaling the presence of a ``hit". When the S/H pulse is applied, this transition is driven off-chip via a series of inverters.
The TH_SEL switch is used to increase the value of C9 by a factor of 5, thus providing a larger range of threshold settings.
Figure 3.: Circuit diagram of the discriminator.
Figure 4 shows the charge driver circuit. It consists of two well-matched source followers that have two capacitors, C6 and C7, across their outputs. The capacitor C7 can be removed from the circuit by turning off the GAIN_SEL switch; in the following discussion we will assume that this is the case. In order to understand the functionality of this circuit, we need to examine the overall operation of the SIFT chip, which consists of a RESET cycle (about 1 us) followed by up to 56 ACQUISITION cycles (132 ns each), depending on the number of bunches in the Tevatron ring.
Figure 4.: Circuit diagram of the charge transfer block.
The RESET cycle is initiated about 300 ns after the SVX reset and it starts with the PRST, DRST, READ and PCLP switches closed. After 10 ns, PRST is released and the output of the preamp undergoes a transition determined by VDR. We allow the output node to settle and after about another 50 ns the DRST switch is released. This causes the THSET pulse to cause a small transition at the preamp output, the size of which is determined by VTH. Both of these transitions do not have any effect on the outputs of the source followers (SF1 and SF2) in the charge driver circuit because they are held during this period at known values controlled by an external voltage (VCLP). The only difference in the output results from any difference in the gains of the source followers. Meanwhile, the capacitor C6 and other stray capacitors (to ground) are charged by the SVX reset current. The voltage on C6 is equal to the difference between the SVX input bias and VREF. Now the READ switch is opened and the S/H switch is closed. The capacitor C6 now registers the voltage difference between SF1 and SF2. At this point, the PCLP switch is opened and the circuit is ready for acquisition.
During the ACQUISITION mode, the preamp is reset after every bunch crossing. In order to minimize any injection at the source followers, PCLP is also exercised during the preamp reset as shown in Figure xx. Any charge at the SIFT input causes a transition which is fed into SF1 by the buffer amp and is duly recorded on C6 when the S/H switch is closed. At this point the sampled charge can be transferred to the SVX by opening the S/H switch and closing the READ switch. As mentioned earlier, the voltage VREF is chosen so as to offset the dc bias of the SVX input. However, due to variations in the dc bias of up to 30 mV unwanted charge is injected into the SVX, the size of which is given by the output capacitance. Hence, including C7 into the circuit doubles this injection. Also, charge can be injected into SF1 when PCLP is released. The size of this injection depends on VDR and VCLP. Hence, for minimal charge injection, these two voltages as well as VREF need to be tuned experimentally. This will be discussed in great detail in section IV.
III. Test Results
The chip has been put through extensive bench tests. The test setup consists of 4 SIFT chips and an SVXII chip mounted on a printed circuit board, a TeK DG2020 arbitrary clock generator and a VME based SVX readout system that is controlled by a PC. The DG2020 is triggered by the SVX readout system and produces all the control clocks and an input signal for the SIFT. The input pulse has been used in two different modes, first as a voltage impulse across a coupling capacitor and second as the trigger to an optically coupled current impulse circuit. The results from the two were found to be consistent.
Figure 5 shows the performance of the discriminator circuit as a function of the threshold setting. It can be seen that the variable threshold of the SIFT chip is linear with respect to the input charge. Due to internal time constants in the chip, the response is also a function of the arrival time of the input charge. Effectively, the gain of the preamplifier is reduced for late charge but remains linear. We also tested the behavior of the circuit as a function of the bunch crossing number following the reset. We found no dependence as shown in Figure 6.
Figure 5.: A plot of threshold voltage required for 50% turn-on of the discriminator 50% as a function of the input charge. Various curves represent different arrival times for the input pulse.
In order to evaluate the overall efficiency of the discriminator, in Figure 7 we show a blow-up of the small charge region. The line marked "noise level" indicates the threshold level required to completely turn-off random noise firing of the discriminator. In this case, we pulsed the S/H 1 million times and did not get a single output. This test is quite stringent but conservative enough for this important measurement. As can be seen, the smallest threshold that we can set (so as to stay above noise) is 3 fC for prompt signals and 7 fC for signals that arrive 60 ns after the beam crossing. Hence, we can comfortably set a threshold such that the chip will fire the discriminator on single photoelectrons.
Figure 6.: A plot of threshold voltage as a function of the bunch crossing or "pipeline" number following the reset cycle. The input charge was kept constant.
Figure 7.: A blow-up of figure 5 showing minimum threshold settings above noise.
Charge transfer and gain calibration
Figure 8 shows the charge recorded by the SVX as a function of the chrarge input to the SIFT. The saturation at about 460 fC is not due to the SIFT but because the pipeline amplifier in the SVX is getting saturated. Figures 9a and 9b show straight line fits to the linear region. The two plots correspond to two settings of the gain selection switch which provides a factor of 2 difference in gain. From these plots we can deduce that the charge transfer from the SIFT input through to the SVXII output is very linear. For reference, one photoelectron from the fiber tracker is equivalent to a charge in the range of 5-8 fC. Hence, the chip can handle 60-90 photoelectrons without saturating while the mean number that is expected from a minimum ionizing particle is only 10 photoelectrons.
Figure 8.: Charge transfer measured at the SVX digitization stage as a function of SIFT input charge.
We also carried out a calibration of the output capacitor. This was done by feeding back the output of one channel of the SIFT to the input of another and using the threshold setting as a measure of the output signal. We calculated that the capacitor has a value of 85 fF, which is very close to the design value of 78 fF once the strays are taken into account. This fact will be very important as we discuss the issue of unwanted charge injection.
Figure 9.: Straight line fit to the charge transfer between the SIFT and the SVX. The gain select switch provides a gain difference very close to a factor of two which was the design value.
Minimization of Injection and Tuning of Voltages
The results shown here have required some tuning of the voltages that control the SIFT. Of particular concern is the charge transfer circuit that dc-couples to the SVX. Figure 10 shows the out put of the SVX preamp after tuning of voltages. Each "spike" in the wave-form represents a READ pulse to the SIFT. As can be seen, there is no net injection and the overall waveform is flat. Figure 11 shows the response when the SIFT is injected during three different crossings. The step ladder waveform expected from a charge sensitive amplifier is evident.
Figure 10.: SVX preamp output waveform under the net zero injection condition.
Figure 11.: The same condition as figure 10, except that the SIFT was injected with charge during three different bunch crossings as shown. There is still no injection in crossings in between the various inputs.
Figure 12: Effect of raising a) VCLMP, b) V_DR and c) VREF. Net injection occurs.
The effect of raising any of the three voltages VCLMP, V_DR and V_REF is shown in
Figure 12. Net injection results in each case but not always with the same polarity. From this one can infer that the voltages can always be tuned within their specified range and a zero-injection situation can be achieved. As mentioned earlier, the output capacitor was measured to be 78 fF, and quite safely to be below 100fF. If the variation of the SVX bias is 30 mV peak-peak, then the maximum injection per cycle would be 3 fC. However, we expect the variation to be small on any given chip and we plan to use the tuning to minimize the injection.
Finally, we can look at this injection issue more quantitatively. Figure 13 shows the response of the SVX to three input pulses occurring during three different bunch crossings. Note, that the SVX pipeline numbers decrease with increasing time, and hence, P20 represents the earliest pulse. We can not discern any difference in the response to P13 and P6, but they are both somewhat higher than P20. This could be due to some slow recovery from reset in the SIFT. Also, once again, the saturation of the SVX pipeline amplifier can be seen.
Figure 13.: Response of the SIFT+SVX to three inputs during three different bunch crossings. No large effects due to pile-up can be seen.
Next, we injected many more pulses in order to saturate the SVX preamp. Figure 14 shows the series of curves. Recall that P23 is the earliest and P2 the last. The effect of saturating the SVX preamplifier can be seen clearly. For instance, after 6 pulses of about 175 fC each, the seventh pulse (ie, P2) saturates the preamp. Similarily, after 5 pulses of about 225 fC each, the sixth pulse (ie, P6) saturates the preamp. We can extract information regarding injection from these plots as well by plotting the sum of all pulses as shown in Figure 15. The saturation which had started at about 450 fC with P13 is reflected in this curve which also saturates at about 450 fC. If there was large injection between P23 and P13 (10 crossings), then the curve would have saturated earlier.
Figure 14.: response of SIFT+SVX to seven different inputs. The effect of SVX preamp saturation can be seen.
Figure 15.: The sum of all the outputs in figure 14. The saturation occurs at the same stage as expected which shows the absence of large injection.
The SIFT chip has been extensively tested for performance criteria dictated by the central fiber tracker requirements. The discriminator is linear. Effective minimum thresholds of 3-7 fC can be set. The charge transfer circuit is also linear. With some care and implementation of external circuits the spurious injection can be kept to a minimum.