Fiber Tracker Emailed Update

talk slides as given at the Stony Brook group meeting. Comments written in the summary email from Marian follow below.
We made a plot which shows the dependence of the cluster efficiency on the size of the window around the track where we look for a cluster that could be picked by the track reconstruction algorithm

The point we are looking for is where the efficiency starts to plateau. Formerly, we have used 3 sigma ( 3 x 125 um ) which was a little bit underestimating the efficiency. Our reasoning was that 3 sigmas are basically ~99% of the signal.
The plot you can see was done for layer 10 ( 5th cylinder, stereo layer ). (It can be provided for other layers too)
The number we have chosen is 6 resolution sigma.

Given this definition of the CFT cluster efficiency, we have studied 2 samples :

There are 4 files which show the results ( eta and phi both for 20 ADC cut applied and removed ):
phi efficiency with 20 ADC cut
phi efficiency without 20 ADC cut
eta efficiency with 20 ADC cut
eta efficiency without 20 ADC cut
- The first plot in each file shows the multiplicative product of efficiencies in all axial layers ( 7 layers ).
- The second plot shows the same product for all stereo layers.
- The third plot shows the multiplicative product of all layers ( both axial and stereo ). This plot tells you what the cluster efficiency of the entire detector would be if we always required all hits to build a track.
- The last plot is again the multiplicative product of efficiencies for all layers but this time we allow 2 misses. This is why the efficiency is higher. You can see that the dip in eta around zero gets smaller when we start to allow misses. It does not disappear when the 20 ADC cut is applied however. You can still clearly see it.
- Compare the fourth plots with the ADC cut applied to the sample where the 20 ADC cut was removed - the situation is much better with the cut removed. The dip almost vanishes. In this case only the hardware cuts affect cluster efficiencies.
It would be nice if we could perform some comprehensive study and tried to optimize the ADC cut so that we get closer to the hardware cuts only scenario.