Reply to the 'Review of the DZero CTT Upgrade Proposal (4/8/04)' v2, jo/mj/sg 2004-04-20 ============================================================================================ 48 V power system: ==================== We have followed the recommendations of the committee regarding testing and up-front engineering. The 48V system has been tested and CAL doesn't see any noise from a single converter. Mode locking is not a problem with these converters; but nevertheless we're adding extra filtering/shielding to prevent any crosstalk between converters. Marvin comments: " I am personally a little worried about the 48 volt system because we are so noise sensitive and 48 volts is a lot of amplitude. However, I am also well aware that we cannot always reject solutions just because of a worry. I am happy with the 48 volt solution provided we add good EMI shielding to the converter. This is the current plan." Crate Controller and download interface: ========================================== We are following the recommendations, and are adding a parallel port. We are also adding a second prototype to the schedule. For schedule impact see the project file and also the shutdown planning comment below. OSU board: ---------- Maybe we were not clear enough in our presentations: the OSU board is a similar project, but by no means a drop-in part. The OSU board cannot be used in our application. It lacks the SCL receiver, and furthermore it would force the DFE boards to implement a full VME interface. The FNAL and BU engineers agree that full VME would be overkill, plus it would not be backwards compatible with existing DFE hardware. In addition, keeping the dfe backplane busses synchronous with the beam crossing frequency will reduce the chances of injecting noise into the cal electronics. No off the shelf controller can do that, not even the osu board. Marvin comments: " I had thought of a hybrid solution for the crate controller using a commercial VME module like the L3 single board computer and just designing a small PMC card for the SCL. I rejected it because it transformed a simple hardware board design into one that requires a lot of careful software (including a new driver). If we were to pursue something else, I would investigate this more thoroughly. However, the software to handle the SCL interrupts correctly would take a good bit of effort. I really don't see that one is a lot easier than the other and we have the engineering expertise and we do not have the software expertise. In addition, there is the 16 MHz VME clock that we would have to contend with as far as noise shielding. " Gigabit Ethernet: ------------------ To clarify the '12 hour download' problem: the problem is not that the download takes 12 hours (even though that would be annoying and get in the way of efficient firmware debugging). The problem is that the probability of having zero noncorrectable errors during a 12 hour period approaches zero. So, one can debate how often one really needs new firmware (we claim that we actually do want to switch quite often between special diagnostics and the then current prototype firmware), but we need to be able to download at least one version successfully. The error statistics for the current system shows that it's just not a viable option for the larger chips. The reviewers argue that implementing a gigabit ethernet interface is too much of a technical risk. As a fall-back contingency feature, we will be adding a parallel port to the new crate controller. (Using the parallel port will probably be about as fast as the current 1553 bus, but it's an option.) Splitter Board: ================ John Anderson has identified the manpower for designing and laying out the splitter board, and work is in progress towards the first prototype. We have added a second prototype to the schedule. Fall 2004 shutdown planning: ============================= I think we are in better shape here then the reviewers assume. Due to the initial decision to decouple the new and the old system by building new crates and motherboards, we have a great degree of flexibility as to when we install components for test. Specifically, for the Fall 2004 shutdown all we really need to achieve is installation of a new crate with power supply and backplane, the LVDS cable extensions and the splitters. Crate controller and DFEA prototypes can be added (and replaced) during shorter accesses later. We fully agree with the committee that comprehensive testing outside the collision hall needs to be done. To that end we have asked for extensive test features (I/O seed and capture buffers) to be designed into the new DFEA. However, we still know from experience with the current system that there is no replacement for testing in situ, especially with regard to timing. This does not mean that one should neglect the full timing simulations that we have been advocating. Backplane pinout: ================== Frankly, I think it's one of those cases where a buck saved now will cost us ten or hundred fold in the future. Debugging the cable plant, even with proper labels, is one of the most frustrating and error-prone aspects of system installation and maintenance. I'm afraid I have to insist on proper separation of input and output cables, even if it complicates board layout somewhat. I don't see any need to repeat mistakes of the past. If there is a trivial cable ordering, we should use it. So, let's avoid input-output-input schemes, or 0-1-3-2-4 link ordering, etc. etc.. A local backplane engineering review will take place this week. Schedule and 'Jamieson Normalization': ======================================= As I stated in the review, Jamieson had properly taken into account that there is only one copy of himself when he estimated the duration of various overlapping tasks while still supporting the Run 2a system. I did NOT attempt to preserve that normalization when entering tasks into the project schedule. I will try to correct that in a new version, by assigning proper resource percentages. Milestones: ============ I have reduced milestones to 0 day length. Milestones for 48 V and backplane pinout decisions have been added.