Scope Shots from New Interface Board Testing

• Turnon:

SVX Power turnon 

• Mode lines:

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Readout

Clocks vs Priority_in

• Dvalid - 30' sequencer cable, no clock pulse shaping, kludge adapter on SASEQ, use 7612-300 with clock resistor installed. Checks on IB#1.

Dvalid vs D7 at SASEQ

Dvalid vs D7 old 6U board, at SASEQ

Dvalid vs D7, SVX side, @ IB

Dvalid delay (SVX side of IB, and at SASEQ input)

Dvalid vs data lines: 75 ohm series termination, SVX side

1. Comments on running conditions and location of measurements (2/29/00)

2. Dvalid vs D7

3. Dvalid vs D6

4. Dvalid vs D5

5. Dvalid vs D4

6. Dvalid vs D3

7. Dvalid vs D2

Dvalid vs data lines: SVX side, with parallel termination (a la Aurelio)

1. Comments on test conditions and resistor values used (3/10/00)

2. Dvalid vs D7

3. Dvalid vs D4

4. Dvalid vs D3

5. Dvalid vs D2

6. Dvalid vs D1

7. Dvalid vs D0

Dvalid vs data lines: quasi_AC termination, SASEQ side

Running conditions and location of measurements (SASEQ cable at kludge adapter)

1. Dvalid vs D7

2. Dvalid vs D6

3. Dvalid vs D5

4. Dvalid vs D4

5. Dvalid vs D3

6. Dvalid vs D2

7. Dvalid vs D1

8. Dvalid vs D0

EXCEL screen shots:

9 chip HDI (3954-220), charge inject, 25 evt (2/00)

Updated 3/6/2000 ras