Subject: Rev 3.2 Files Date: Wed, 8 Mar 2000 16:42:54 -0600 From: "Russell D. Taylor" Reply-To: KSU D0 Project , "Russell D. Taylor" To: KSUD0-L@LISTSERV.KSU.EDU HEP008 (Interface card) Rev 3.2 files are on the EDL website at: ftp://saron.edl.ksu.edu/pub/fnal/Rev3_2 file name is HEP008 REV 3_2.ZIP A change history is listed below. If anyone has questions or comments let me know. Sincerely, Russell D. Taylor 1. AVDD on indication voltage level changed to 3.0 volts 2. DVDD on indication voltage level changed to 3.0 volts 3. +5v voltage reference changed to more accurate lm4040, also required resistor change. 4. Ground unused dedicated inputs to Altera chips. 5. Ground master reset pin of Manchester adapter (pin 13). 6. Changed 1553 transformer center tap voltage of 1553 circuit to 9v, using lm317 regulator circuit. 7. Added 3 Watt resistors in line with power to center tap of 1553 transformer to provide current limiting protection. 8. Changed 1553 circuit from time out operation to full time operation (stuff different zero ohm resistor.) 9. Change minimum current of clock shape offset voltage regulators by changing bias resistors to lower values. 10. Corrected connection of feedback resistor to output of amplifier on AVDD current differential amplifier. 11. Corrected .47 uF capacitors to all be of 1206 size. 12. Corrected component values of several resistors that were indicated as 5% to the 1% values actually used. 13. Vcc to 1553 oscillator is tied to /OI on the 1553 Manchester encoder to disable the outputs when the oscillator is not running. 14. Added buffer enable to the status bits, signaling that the entire channel is up and ready to run. 15. Changed Data line terminations towards SVX to 24 ohm series, 91 ohm parallel as per Aurelio. The 91 ohm resistor required a resistor size with a greater power rating. 16. Added 300 ohm resistors across the 1553 line switches for increased transformer reaction. 17. AVDD, DVDD, AVDD2 analog inputs voltage dividers to be 8v full scale at five volts input. 18. Corrected AVDD, and AVDD2 alternate grounding option. Was supposed to be zero ohm possibility to digital ground. 19. Added possible mounting points for a shield around the 1553 transformer. Also left 3/8" clearance for shield. 20. Spaced apart 2n3725 1553 BJT switching transformers to allow heat sink attachment. 21. Fixed clearance on 80 pin connector to allow AVDD, DVDD, AVDD2 greater space between pins. 22. Fixed clearance problem on 15v input. 23. Changed faceplate mounting holes. 24. Changed numerous silk screen label locations. 25. Added test points for data and control signals. 26. Extended ground copper pour around 80 pin connectors. 27. Added a second digital ground for a 10th layer. 28. Changed layer order. 29. Made all signal traces on layer4 and layer6 5 mil wide. Russell D. Taylor Electronics Design Lab Kansas State University 124 Burt Hall, Manhattan, KS 66506 785-532-2093 rdtaylor@ksu.edu fax:785-532-2092