Minutes -Interface Module Group 4/22/99
---------------------------------------
Attending: Sobering, McDavitt, Sidwell via telephone; Reay, Fogelsong,
Leflat, Zverev.

A very short meeting.

Foglesong: needs a draftsman for drawings, which he hopes to get by next Wednesday.

McDavitt- has new front panel layout, with miniature coax shown. Current
   problem is that the mini-coax connectors are board mounted, so that
   cabling is not straightforward. The drawing will be posted anyway on the web site 
   for folks to see. Also this drawing has no front panel, and thus no ejectors.
   Sidwell stated that ejectors are required (more than 300 pins are plugged in).

LV- distribution. Some discussion of Marvin's email to put a voltage regulator,
	current limiter on each HDI. For 24 regulators (3 voltages, 8 HDIs)
        this would use ~48 sq in (or more) of a useful total of 112 sq in.
        Also heat sinking may be a problem. Marvin's note is attached below.

    Sidwell showed the following:

Calculation of Voltage Drops: AVDD1							
					R(ohms)	
1) Power leads to Interface Module      0.013

2) Interface module:		        0.924	
 email Leflat 4/21/99							

3) 3M cable			20'	1.100	 NRS, 30 gauge x 2 wires

4) Stripline			8'	0.370	

5) HDI tail				0.333	
   (typical 9 chip)
				Total	2.76 ohms

AVDD1 Model:		Range needed 4.9-5.2v				
I/chip=	0.023	 before download				
I/chip=	0.046	 after download				
Nominal supply= 5.05v at SVX chip						
# SVX	        Drop(v)		Supply 
3		0.38		5.43		
6		0.76		5.81		
8		1.01		6.06		
9		1.14		6.19

Thus for 9 chip HDIs the voltage needed at the supply is 6.19V, and
the total drop (after download is done) is 1.14V.		
 
Sidwell promised to put this on the web site, with a sketch of power distribution
panel, etc. The simple idea, is to have a separate supply for each class of
HDIs (3,6, 8,9 chip). We need to lower the total resistive path, to < 2 ohms
if possible. 

Later questions and comments from Marvin:
1) current limits on close packed cables - this is an ES&H issue
2) how well does the diode termination work with direction reserved (the
bus is bi-directional). 
3) Current fluctations as a fn of time. 
4) Problems with ground connection on existing 3M cables.


To do: 
1) Get scope traces of transient power draw (few ms scale) to understand
what happens during turnon and data digization.
2) Decide on connectors from front panel. Post exist drawing and email to
Foglesong. (McDavitt for drawing, others for decision!)
3) Drawings of cable runs, and other items (Foglesong)
4) Crate, slot layout of detectors (Sidwell)
5) Photovoltaic relay tests (Matulik)