Minutes - Interface Module Meeting May 27, '99
---------------------------------------------
Att: Foglesong, Johnson, Lipton, Matulik, Reay, Sidwell, Utes,
and via telephone: KSU EDL, & Stanton.

1) Space, cable routing, etc: Foglesong
John had new drawings showing proposed cable routing,
and HV general distribution. These will be posted on the web site as
soon as available to me. Marvin expressed concern that there is only 21"
available above the crates for card removal and cables and urged us to
get moving with a mechanical mockup. The interface module cards are now
oriented perpendicular the beam.
 
2) J1 draft layout: Jensen
    Scott had a draft J1 layout (see web page). Scott was requested
to mark the SVX power pins on the drawing (e.g. AVDD, etc).  

3) Updates on low mass cable and other cable issues: Stanton
   Main new issue was delay between clock and other signals; which is
calculated to be ~5ns (the clock runs on coax and is early). It was 
suggested we would need a lump delay on the interface module for each
clock/clock-bar pair (16 delays @ $7 ea).

4) Further termination studies- Mike Utes
Mike showed signals from additional studies of resistive terminators, with
a small series capacitor (70 pf on the ground side in series with 160-ohm),
a psuedo-AC coupling. Signal quality looked good.

5) Request for volunteer to survery voltage regulators:
would need 24/module, range 3-8 volts, 1 Amp rating. Johnny G said
he may be able to do this.

6) Discussion of feasibility of schedule
-----------------------------------------------------------
Rough schedule for Rev 3 production: backplane and module:

   June............ complete design specs
   July/August..... schematic and layout
   September ...... assemble first IF crate w J1, J2, J3 backplanes
   September....... produce eight 9U cards for 10% test
   October......... debug and revise cards
   November........ let purchase order for ~150 cards
   Jan 2000........ receive order
   Feb-April 2000.. testing, debug cards

Tim Sobering stated, after the meeting that a more realistic schedule
would be:
 Decisions on Termination,
        Connectors, 1553, SOH,
        Voltage control (HV/LV)  (4 weeks)
     Finish schematics           (3 weeks)
     Layout rev 3                (6 weeks)
     Fabrication - 135 boards    (4 weeks)
     Stuff 135 boards            (4 weeks)
------------------------------------------
     Total                        21 weeks  (mid-October)   
The start date on this schedule was ~May 21.

We have yet to address monitoring and 1553 functioning. Marvin
regards the question of voltage regulators as a major concern.

7) Other business:
    Safety: cables should be flame retardant (except where very low
current such as bias voltage) and halogen-free. Power supplies need
to be fused or otherwise protected against shorts. 
    Sidwell was strongly urged to summarize design decisions to date.

   
8) Next meeting June 10, 3pm, Salle des Heros