Interface Card Meeting Minutes 3/25/99
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Present: Foglesong, Johnson, Leflat, Matulik, Reay, Sidwell, Zverev

The major part of the meeting was occupied by trying to establish
baseline parameters for card size, crate size and orientation and other
logistics.

The following consensus was reached on design parameters:

Proposed card size: 9U x 220mm, 8 channels (HDIs) per card

Crate size: modified 9U (reduced depth!)

Crate count: 2 per corner under the calorimeter (total of 8). Each crate
would contain either 14 or 15 IF cards.

Card spacing: standard VME (0.8")

Crate Backplane: custom, similar to Sequencer crates -
     4 sequencer connectors, 1553 interface, LV (+5,+15,-15),
     SVX power (AVDD, DVDD, AVDD2), Bias voltage connector (8/card)

Crate Orientation: with cards perpendicular to beam. Sequencer cables
     plug into back of crates; output is on edge furthest from beam.
     Two crates will (space permitting ) be stacked vertically.

Access to back of crate: crates should slide out perpedicular to beam.

Space budget (depth):   cards      9"
                       connectors  2"
                       cables      6" divided between front & back
                       clearance   4"
                                  ---
                                  17"

     Note: 21" is available, less "keep clear" requirements.

IF card power: currently 0.5A @ 5v per channel, thus 20 watts/card.
     For planning assume 600 watts per crate. 

IF power supply: 200 A @ 5v (switching) per crate. Total=8 supplies. 

Crate cooling: unspecified


Discussion of current limiting: The issue is can we avoid use of fuses 
on the IF card. Teststand experience shows these blow constantly. One
is trying to protect the wirebonds which bring power to the SVX chips. 
Evgeny showed measurements of the breakdown point of these to be
~3/4 A. (See transparencies). Leflat proposed a scheme using logic 
circuitry to cut power when limits are exceeded. He was urged to pursue
this matter. In addition it was recommended that wire size be increased
for these wire bonds- a factor of up to four is possible by using larger
diameter wire. Pads for the SVX power have ample room for larger wire.

Discussion of Silicon detector Bias voltage: 
 (Range of depletion voltages is from 0 to +-200 V, bias current range
from tens of nA to a few mA)
The baseline design is to recycle VME4877 high voltage modules from Run I,
using one HV pod per 4 detectors. Cable path would be: SHV cable to 
patch panel. Then HV lines are bundled at the patch panel via a Renolds connector 
to shielded cable with 8 conductors (96 cables = spares). These cables run
to patch panels near the IF crates, where two lines are broken out
per IF card to carry the bias voltage. Fanout of HV must then occur on the IF 
card, and if control is desired would require HV relays and support logic
on the card. No relays have been located to performm this function, in the
300 G environment. 
 
Sidwell proposed a separate input for each detector (768 would be needed),
with fanout occurring in the Moveable Counting House (MCH), and no HV
control on the IF card. Marvin suggested that twist & flat ribbon cable 
would then be used from the MCH to the calorimeter and that current 
measurements by detector would be available on an as needed basis using a 
diagnostic 4877, and moving a cable to it.
Any further customization and single detector support would require a new
HV system altogether. It was stated by Marvin that the CDF HV system from 
CAEN cost $350K. 

Fogelsong stated that there was insufficient room in the MCH house for the
proposal, and in the cable trays.

Jobs:

Foglesong: Update drawings showing proposed crate configuration, and
    also adding location of cable cutout in muon iron (so we can understand
    cable routing better).

Sidwell, Reay: Try cable routing schemes with 16 seq cables, to understand
    clearances needed, and turns to be made. 

Johnson: Marvin, in absentia, was requested to recommend a crate cooling
    expert.

KSU: specify Bias voltage connectors and distribution.

Sidwell: begin project definition documentation

Sidwell: setup up web site for organization of documents, schematics,
    minutes, etc. Currently these are found at:
    d0server1/projects/smt_teststand/documents/interface_card

Leflat, Zverev: research current limiter suggestion using Alter PLD

--> Rev 2 IF card testing: hold off stuffing for another week. 
    Sasha and Evgeny have some proposed changes in several resistor
    values, and other components ( swap Ge for Si diodes). 


Next meeting: 3pm April 1