Notes on Interface Module Design Review 7/29/99
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Present: Utes, Matulik, Johnson, Reay, Lipton, Rapidis,
Zverev, Sidwell, and Russel Taylor.

Board Count: Decision to fab 12 boards, and stuff 2 for intial tests in
September. Order parts for 12. We need 9 boards + 1 spare for
full-barrel test (aka 10% test); and the other two would be in use for
revisions, further tests, software development, etc. The first 12 boards
not likely to be used in the experiment.

Parts buying- go ahead with orders thru KSU for 10% test. Order
balance of long-lead time items thru Fermilab.

Kludge area: none planned 

Clock pulse shaper: request to put on a daughter card for
customization for 3, 6, 9 chip HDIs if needed. Under consideration.

DESIGN CHANGES:

--  Primary and secondary bias analog inputs will be removed. ( This will
also reduce the 1553 message by 1 word. )

--  Analog to digital converter will be operated in uni-polar mode.

--  -15 volt supply will be removed from the board.

--  Use a Sallen and Key 10 Hz. filter on the input to the current limit
comparator.

--  Adjust the temperature output to measure -15 to 100 degrees Celsius
from 0 to 2.5 volts.

--  Add a 50 degrees Celsius temperature trip input to the power monitor
PLD.  The circuit should not trip due to an open or short circuit. 
We can add a bit for this on the state of health byte. Power monitor PLD may
need to be resized.

--  Use only a single fuse on the VCC power input.

--  Add 10k resistor to ground on the positive op amp input of the cal
voltage amplifiers.

--  Add a jumper in line with Primary Bias after the  relays and decoupling
capacitors.

--  Change the Priority out comparator threshold to .7 volts on the rising
edge.  ( Can someone tell me what termination this was found with?)  The
negative edge threshold is to be determined.

--  Fab 12 boards but have only two stuffed.  The remainder of the boards
will be stuffed when the design is verified.

Additional Suggestions

--  Use Instrumentation amplifiers instead of op amps to reduce resistor
count.

--  Use a 8 channel multiplexor for analog inputs instead of the 16 channel
multiplexor.

J1 Back plane

--  Devise better solution for power inputs.

--  Use jumpers to connect various ground types in the ground plane to
increase ground scheme flexibility.