Minutes - Interface Module Meeting July 15 '99
-----------------------------------------

Lab A Conference room, July 15 '99
   Attendees: KSU EDL, Reay, Lipton, Johnson, Green, Utes,
Zverev, Stanton, Russ Taylor, Bolton & others.

Status of design & schematic: R. Taylor

   Some work remains on Altera pinout and programming, and 1553 
termination.

Decisions and design changes requested:

  1) Trip level for current limiters:625mA. Trip can be as
fast as possible (no need for ordered shutdown). Time constant
to integrate signal should be > 20ms (of order 60Hz) so as not 
to trip on glitches.

  2) 8 bit ADC limits: 
     1A on currents
     8v on power voltages
     +-150v on bias voltages

  3) Power up logic (raised by Zverev). AVDD turn-on feedbacks
to AVDD2 comparator sometimes, and AVDD2 then does not turnon.
The SVX supplies are not truly isolated.

  4) Request amplifiers, with gain of 1.2X in the Vcal lines 
(after fanout). This decouples the HDI chains. Note that there
are separate Vcal_a and Vcal_b lines on the output 80-conductor
cable.

  5) Dvalid first pulse has anomalous width (~12ns, compared to 18 
or 19ns). Mike Utes will investigate. Proposal is, pending Utes
investigations, to add a one shot to dvalid to standardize pulse
width. Note added: Mike has investigated and recommends a pulse shaper
for Dvalid.  

  6) Dvalid delay: leave wire for delay to possibly be added.

  7) Clock, clock-bar delay. Remove! This will be handled by
the sequencer as needed.

  8) Terminations:
     a) put thevenim or 75 ohm to ground on clocks (waiting on 
recommendations from Stanton).
     b) ABT- HDI add diode pads on cable side of series resistors
  for data lines
     c) Priority_out: keep comparator.
     d) Dvalid: terminate like data lines.

 9) HV grounding: wait on schematic from Foglesong (but leave
as it for the moment). HV lines are supposed to be isolated at
the supply.


J1 backplane: mechanical drawing and schematics will be turned over 
to Pat Sheahan, who will locate vendor for final engineering and
fabrication. 

 
Production Schedules: Sobering, Taylor
     No particular comment. Goal is 12 boards by Sept 14.

Updates on low mass cable and other cable issues: Stanton?
    Will hand over low mass cable setup to Marcel. Discussion
of orders for 10% test.

Mechanical mockup status: Sidwell (5 min)
     Plan to have crates ready week of July 27.
 UPDATE: still waiting on delivery of 80-conductor connectors,
not expected until early August. The entire order for these 
connectors (~$5000 has been placed).

    
Schedule next meeting: July 29  Final Schematic & Design
  Review (if ready); followed by a Layout Review when that
is ready (target is ~Aug 20).