Dear All,

According to our schedule, FPD integration to D0 DAQ 
requires to do some effors in order to use AFE and DFE
boards, which are used as a trigger discriminator.

AFE board installation must have two specific steps, 
represented by two boards, denominated as FSDB 
(FPD Serial Delay Board) and TPP (Transition Patch Panel.)

We need to concentrate effors in order to get the proper 
configuration to use AFE. The, the next step woul be to go to 
the AFE Test Stand and look is FPD signals are making trigger 
into the SIFT.

Attached the minutes of our meting on June 21st, 2002.

Regards,

Ricardo 


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AFE - DFE for FPD

June 21st, 2002	8-9 AM

- Presents:

Mario Vaz (phone), Newton De Oliveira, Pierrick Hanlet, Anton Smith, 
Andrew Brandt, Carlos Avila, and Ricardo Ramirez


- Agenda:

1) TPP Board 	-> Pierrick			<-> 15'
2) TPP (Test)	-> Carlos and Newton		<-> 15'	
3) FSDB 	-> Mario, Anton, and Ricardo	<-> 15'
4) DFE		-> Mario and Ricardo		<-> 15'
5) Other issues -> All				<-> 10'


- Minutes

1) TPP Board

Pierrick asked to check is it is possible that Charge is beign piled up 
into the TPP board. A possible solution is to use the SIFT reset in order 
to empty the charge that remain in the capacitance.


2) TPP Board (Test)

The board has been tested for differents Amplifier Shapers. ALso, some
PSPICE simulation have been used in order to find the value of capacitance 
required to reach the proper charge for AFE input. 

More studies are required, Newton has suggested to use a diode arrangement 
in parallel.

Also, Carlos is going to ask for help from Paul Rubinov. Carlos is planing to
stuff the Board.

Mario is goign to send us a SPICE model of SIFT. It will be very useful 
in order to have a model closer to the real implementation. 


3) FSDB

Anton has been working close enough to John Anderson. They are looking 
for a solution in this required delay. Multiple ideas has emerged around this 
issue, but we have concluded that FPGA solution is the best option. 

We are going to test the Mario's model which has been coded for one delay line.
The implementation has had some problems using INOUT buses.  However, it cannot 
stop us our tests. By now, we are going to go around testing a single line.

4) DFE

Ricardo does not have make progress in this issue.

FPP L1 firmware will have three parts, as far as we know, they will be Receiver, 
Body of Calculations and Sender. The Receiver is the same that CFT is using for its L1
trigger. The Body of calculations corresponds to the instantiation of 
Mario and Wagner's equations. Finally, the sender is a new module that requires to be 
design. The sender will put its information in TM.