Verilog Frimware files
Brendan's Message
Chan_FPGA	rampointerver14.v
	singlechannelver14.v
	twochannelsver14.v
VME_FPGA	vmeaddress_13.0.0.v
	vmemodulever_13.0.0.v
VTX_FPGA	get32from8ver9.v
	lm0ver10.v
	pick32ver9.v
	rank4ver9.v
XCK_FPGA	busyerrorinit_13.0.0.v
	rampointer_13.0.0.v
	xckmodule_13.0.0.v
Xilinx Implementation
December 20, 2002	Schematic + Verilog (Fundation 3.1)