FY98Q4
Jul-Sep 1998

The major accomplishment during this quarter was the successful completion of acceptance testing and initial field mapping of the superconducting solenoid installed inside the central calorimeter. This DoE milestone was met on Sept 30, 1998, only a week later than the January, 1998 baseline date.

Areas of concern continue to center on:

• vendor production rate and delivery of good silicon detectors.
• vendor production and delivery of flexible circuits for both the silicon and fiber trackers.

These are discussed in more detail in the individual sub-project reports. Discussions with current vendors continue. Possible alternate vendors are being sought in some cases, while ways to mitigate potential schedule delays are being studied in order to maintain the current baseline date of April 2000, when the detector is scheduled to be rolled in and hooked up.

Cryogenic system work continued in preparation for the superconducting solenoid cold tests. A heater/flowmeter system and controls were installed in each of the two gaseous helium return lines from the vapor-cooled current leads after they exit the control dewar. This system allows measurement of the helium lead flow during operation of the solenoid. At the top of the control dewar, where the current leads connect to the high current bus, a lucite purge box was installed to prevent the formation of frost. Instrumentation cables leading from the solenoid instrumentation port to the controls chassis were installed and terminated. The development of cryogenic control software continued with emphasis on satisfying requirements for the upcoming tests such as the acquisition of quench and cryogenic data. Cryogenic and mechanical safety documentation was finished and appropriate meetings and inspections were held with the DØ Cryo Safety Committee.

The electrical system development included: extension of the high-current bus to the flags on top of the control dewar including flexible copper connections; rejuvenation of the central toroid power system; and instrumentation to measure the resistance of the solenoid during cool down. Preparations were completed for the detection of quenches and extraction of stored energy during a quench, and a final electrical safety review was held to confirm readiness for high-current operation.

In August the field mapping apparatus was installed in the solenoid and in situ tests of the hardware and software were performed. Geometrical survey of the apparatus was postponed until after the magnet tests.

During low-current charging of the magnet the quench detection and protection circuitry was commissioned with the adjustment of both hardware and software based on the resistive components of voltage reported via the voltage taps attached to the coil and magnet leads. Both quench detection/protection and cryogenic data were obtained using fast discharges of the magnet to induce eddy current heating and subsequent quenching of the solenoid. On September 10 the magnet was ramped to 500 A and 1500 A, and on Friday, September 11 the magnet reached its nominal field of 2 Tesla at 4741 A. Magnet tests and field mapping continued until the end of September when it was necessary to end them because of previously scheduled electrical feeder work. During field mapping tests both the solenoid and central iron toroid were powered independently with four resulting polarity combinations of measured data.

The cryogenic data were used to establish the magnet, chimney and control dewar heat loads and to determine them as a function of helium flow in the vapor-cooled current leads. The cryogenic performance results were compared to specifications and were satisfactory in all respects. A slightly resistive joint in the conductor splice in the lower end of the chimney was observed. Although the heat generated by this resistance causes only a 5 Watt heat load, compared with the 30 Watt specification, the joint will require re-splicing at a later date. The field mapping data are being analyzed to understand how to achieve a precise field map in 1999.

A few single-sided ladders with good performance have been produced. However, full-scale production has been delayed by the failure of the flex-circuit vendor to deliver working products (HDIs). Two other vendors have been identified that can deliver tested products on a shorter time scale, although at higher cost. HDIs from one of those vendors are now under test with the SVX readout system. Full-scale production will begin when these HDIs are qualified, laminated to beryllium, and assembled. Also, several mechanical-grade detectors and HDIs were ordered for use in the training of technicians and wire bonders in ladder assembly.

All but one bulkhead sets are in hand, and all beryllium parts have been ordered. Measurements from ladder production show an accuracy of 2 microns. Work continues on the best techniques for in-situ measurements of ladders on bulkheads and the assembly of disk and barrel systems. Coordinate measuring machine systems are in place for all of the detector production work.

A readout system in the "final" sequencer/1553/VRB/VBD arrangement is operating in Lab B. It is read out using both DART and a level-3 based system. Future goals include expanding this system to multiple sequencers up to the level of a full barrel readout, and testing of the system with the final cables and interface cards. This system is also a software test bed for the DØ readout system. Enough detectors should be available for a "full barrel" test in early spring.

There is a new design for the cable system. The conceptual design should be completed in the next few weeks and orders for prototypes of all parts should then be placed. The cables will be included in the 10% test system for a final system test.

A large number of SVX readout systems are needed for detector assembly and testing. The "full DØ" readout system which is available is both too expensive and complex to work well in this capacity. In August and September a new 6U VME module was designed which combined the essential functions of the sequencer/1553/VRB system. This board is currently being "stuffed" and tested in near record time. These readout systems are crucial to the production testing necessary for the DØSMT.

The silicon detector schedule has been delayed about two months by the failure of the HDI vendor to deliver working devices. There is concern that the late delivery of detectors from Micron will further delay the completion of the detector. The current, optimistic, schedule shows final detector delivery nine months after yield problems are solved and full production at the Micron factory resumes. Alternate vendors are being explored for part of the order and technical personnel are being sent to Micron to participate in detector testing.

Prototypes of the carbon fiber support cylinder for layer 3 have been made and inspected. They meet all specifications, so the next step is to make full-length production versions of cylinder 3. The plan is to make three copies of this cylinder - one for mounting tests, one for mechanical tests, and one for the actual detector. Ribbon fabrication R&D is essentially done. All procedures are finalized (except for connector mounting) and the making of test ribbons for mounting studies is expected to begin soon. The ribbon-mounting machine is complete and is ready for calibration, final setup, and programming. Ribbon connector prototyping (curved connector) is being done at two vendors. One vendor has returned blanks that meet specifications. These will now go back to the vendor for final machining of the grooves. The second vendor has not yet delivered blanks to specification. VLPC testing at Boeing is going well. Approximately 40,000 of the roughly 120,000 pixels needed for the experiment have passed testing and characterization.

The major pieces of the support frame (i.e. aluminum ribs, support rings, module boxes, and outer rings) have been rough-cut to size by an outside vendor. The detailed machining of the first two layers of the detector has been completed by the shops at Stony Brook and Brookhaven. Alignment plates and mounting pins to be used during detector construction have been machined and assembled on the two 6' construction domes. The first layer of the detector was precisely assembled on the first dome and the second layer is now being assembled. All 18 km of scintillator needed for construction have been produced, and the scintillator is now being wrapped and its optical properties are being measured. The Stony Brook machine shop is fabricating the alignment hardware for module construction. The first wrapped pieces of scintillator are in hand and module production should begin in late October (Ed. note: Production began on Nov. 4). A vendor for the cast lead/antimony absorber has been identified, final prints have been drawn up, and final preparations are underway for making the mold and the initial lead wedges. The mold for the detector-end connectors has been fabricated, and initial connectors have been produced. The mold is currently being tuned in order to optimize light transmission and minimize channel-to-channel variations. Wave-length-shifting fiber preparation, including rough-cutting, polishing, and sputtering with aluminum on one end also has been completed. Calibration system R&D is almost finished, as is the module test stand which includes a 64-channel phototube and a PC-based readout system.

Bids for the following modules/boards were accepted and the boards are now being manufactured:

In addition, the VRB module test station was completed, the artwork for the VRB controller was finished and the boards are being manufactured, and testing of the cooling system for the new VIPA crates was completed and the plenums for ducting air are being modified

The preamplifier hybrids engineering sample and pre-production 5,000-channel order with Taiyo-Yuden in Korea has been delayed. There have been some communications difficulties with the vendor. The order was placed for the ceramic substrates, but there has been no confirmation that production has started. All specifications for the engineering and pre-production order have been approved, but no request from the vendor has been received for the parts that are in house. A meeting to address the poor communications issues with the vendor is being set up via their local office. One hundred and ten production preamplifier motherboards were delivered during this quarter. These will be tested to see that all pulser traces have uniform capacitance before they are assembled. Testing of a preamp power supply in the sealed magnetic enclosure showed that efficient cooling will be needed to maintain proper supply operating temperatures. Rearranging components in the chassis and adding water-cooling tubes to the modules has begun. Testing of a steel box in the preamp area with both the toroid and solenoid energized showed field levels just below 200 gauss.

A prototype run of new Switched Capacitor Array (SCA) wafers started on the Orbit 6" line. An order was placed for 24 wafers that will be evaluated before more are fabricated. Also, the design was modified to include a protection diode on the one pin that was totally unprotected in the original run. The Orbit design rules were run on the circuit and no violations in their two-micron rules were found. Simple wafer probe testing will be done on these devices. Investigation continued at Accurel, using some rejected units to determine what might be the cause of the offset problem. No visual differences were found. Microprobing within the op amp, comparing good and rejected die, revealed nothing. Cross-sectioning will be attempted as a last resort. Modifications to the design of a large-scale SCA tester burn-in board have begun. These will allow simultaneous testing of both "up" and "down" SCA species.

Most of the shaper hybrid work has been put on hold until the new motherboard design is fully tested. Bid packages have been assembled and sent to several hybrid vendors for production of the shaper hybrids. Vendor questions/comments are now being addressed. The layout of the x1-x8 driver circuit that is compatible with the new shaper design also began. Two solutions are being studied to see which is better suited to the available space.

The first fully functional BLS motherboard has been assembled and testing is ongoing. Testing of the digital part, including the analog storage, has started, along with testing of the first prototype timing and control module. The modified BLS backplane design is complete and the first samples have been delivered. Testing and evaluation is underway, but final approval for production awaits the new BLS Crate Controller who's design has started now that the control signals between the Timing and Control to the BLS motherboards have been specified.

The design and layout of the first prototype testing board for the field-programmable gate arrays (FPGAs) needed in the Timing and Control System was finalized, and the board was built and tested at Stony Brook. The test involved only a fraction of the system functionality since the FPGA design was still not complete. A few problems in the layout and board design are being corrected and a new board will be built.

The prototype design of the pulser system hardware was finalized and two cards (the "command motherboard" and the "active fanout") are being produced and cabled. The fall 1998 test at Fermilab will be performed using the DØ calorimeter test station, and the prototypes will pulse any combination of 96 channels. Results of the November test will be available at the end of the year.

A significant step toward testing of the online calibration software occurred with the development of an interface for transforming GEANT output to front-end data in Run II format. This interface, currently being tested, takes the GEANT output and generates standard ADC pulse heights for each ADC card in a given crate. After testing the interface, the output will be used to test the software in a single ADC crate environment, followed by the extension of testing to a multicrate environment. Initial testing will be done with data files, unlike the real environment where data will come in dynamically. The Level 3 system, where the online calibration software will run, will be upgraded soon. It will add a header/trailer information to the incoming data, but the rest of the data should not be affected. After testing and debugging, the software will be ported to run in a Windows NT environment.

Tests of the final prototype design of the scintillating tiles showed a light yield that met the design criteria, so procurement of the scintillator began. Final changes to the cut tile dimensions were made to accommodate the changes in the tile size due to the final aluminum box design. Wavelength-shifting fiber has been procured, and polishing and mirroring of this fiber for the ICD tile module pigtail assemblies and the calibration fiber in the backplane has begun. Initial tests of the LED calibration system indicated the need for an increase in the light transmission requirements to the phototubes that was within the capability of the system. All four phototube crate assemblies have been manufactured and mechanical drawer fabrication has started. Also, work began on several issues related to the integration of the ICD with the full detector. This included identifying rack space and cabling requirements for the distribution of high voltage to the ICD phototubes, resulting in the need to reduce the fanout/trim board sizes of the high voltage distribution boards. An iron block, crate, and fiber backplane arrived at Fermilab for installation prior to the upcoming solenoid test. During this test, nearly all Run II components of the ICD LED calibration and electronics will be commissioned using the Run II online system.

Counter production continued at Northern Illinois University, where 96 counters were produced during this quarter, bringing the total produced to 274. NIU is responsible for building a total of 270 counters and 16 spares, so production is nearly complete. Counter production also continued at ITEP, Moscow, where 151 medium-sized and 69 large-sized counters have been built. ITEP is responsible for a total of 144 medium-sized counters and 216 large-sized counters, plus spares. A box of 40 large-sized counters from ITEP was delivered to Fermilab in late September, and initial inspection of the counters found them to be of good quality. Two ITEP physicists will be coming to Fermilab soon to do final tests of these counters. Also, design work on the counter mounting system was finished and parts were ordered.

The Glassteel pad replacement was completed in all 22 PDTs that required it. All modified PDTs were outfitted with new service cards and are undergoing leak-checking tests. A total of 30 PDTs remain to be reinstalled on the DØ detector. Indiana University finished production of the high-voltage service cards and jumper delay boards. Approximately 2400 (1200) of each are required. Half of them have undergone the final assembly procedure that occurs at Fermilab. Testing of prototype readout electronics continued using the PDT test stand. One corner board successfully read multiple motherboards, as required, and readout of the MRC into the VBD was also verified. A prototype of the supplemental Low Voltage Power Supplies (LVPS) was built and tested using the PDT test stand. Progress was made in understanding and detailing the cable plants for the detector and 3rd floor movable counting house, and some of the cabling was purchased.

Detailed drawings of the A- and C-layer counters were sent to IHEP and production of the pixel counters started there in August, 1998. The assembly rate is approximately 20 counters per day. Production of the counter case parts used in assembly is well advanced and does not slow counter assembly. There is a potentially serious customs problem associated with the delivery of the remaining 50% of the scintillator to IHEP, however efforts are underway to resolve this problem so that the delay in scintillator delivery does not adversely impact the counter production schedule. Test procedures for the scintillation counters and the documentation of results at IHEP and Fermilab were agreed upon. The test rate of counters should match the assembly rate of 20 counters per day. This rate has been verified using the first octant of counters sent to Fermilab. All magnetic shields and bases were delivered to Fermilab and tests of the bases and their "burn in" are underway at Fermilab. The failure rate after transportation is less than 1%. Long term (> 1 year) aging studies of phototubes and other parts of the pixel counters continued with no major problems found so far. A procedure for selecting groups of phototubes for each high voltage power supply was developed and associated software for this procedure was written. Construction of a full prototype calibration system is nearly complete and testing will begin soon. Detailed calculations of the magnetic forces on phototube shields were performed and the results were published in a DØ Note. While the maximum force acting on any shield at nominal magnet currents is comparable to the shield weight, only a small number of counters are affected. The average force is approximately 10% of the shield weight.

Engineering of the octant frames, octant supports, and counter supports continued. The baseline octant frame consists of an aluminum frame covered on both sides with an aluminum sheet. A prototype has been ordered from industry. Drawings for the octant supports will be delivered to the University of Washington and Fermilab shortly and each shop will make a few prototypes. Production of the counter mounts will eventually be done at IHEP and groundwork for procuring the aluminum extrusions has started.

Detector production was halted in August to investigate the source of large dark currents discovered during testing. Part of the dark current problem was traced to poor wire quality so new, higher quality, wire was obtained from the vendor. However, the dark current problem did not completely disappear and further studies were performed to isolate the source. Preliminary results suggest that the newer wire is acceptable and that the remaining dark current is caused by aluminum dust in the extrusions. Further studies to verify this hypothesis are in progress. Before production was halted, 256 tubes had been assembled at Dubna. Half of these were shipped by air and delivered to Fermilab in September. The remainder is being shipped by sea to determine whether this method is acceptable. The pre-installation test procedures for detectors arriving at Fermilab have been optimized, and construction of production test setups is underway at Fermilab.

Engineering continued on the MDT octant frames and MDT holders (blades). Prototype frames that were welded and bolted did not meet the flatness specification. However, these frames are being used to assemble a prototype octant in order to test its electrical properties. Octant frames that use honeycomb panel structures rather than welding and bolting have been ordered from industry. Prototype polycarbonate blades that hold and align the MDTs were built and tested, and the strength and flexibility of the blades appeared to meet specifications.

A summary of the status of various components of the muon electronics system that were worked on this quarter is given below:

This quarter, a contract for fabrication, parts procurement, and assembly of all SFE cards was signed. Also, 10% of the PDT CB parts were procured. The PDT FEB prototype worked so well that current expectations are to procure all of the PDT front-end boards instead of just 10%, once the 24-channel design is complete.

All of the framework cards arrived except for some of the simple paddle boards which are at the manufacturer. The last big card, the Trigger Decision Module, arrived at the end of August. About 50% of the cards have been individually tested and have met specifications. System integration tests have proceeded and the internal timing distributions are satisfactory. The high-speed readout from the framework has also successfully passed testing procedures. This is especially significant since the readout uses HP G-Links that have under-performed in some other systems. The serial command link hub design is also proceeding. Because of the additional G-Link tests the September ship date was not met. However, the framework will be installed at Fermilab in October.

The assembly of the Luminosity Monitor counters has been completed. A cosmic ray test stand has been assembled and software has been developed to perform data acquisition, calibration, and measurement of the time resolution of a counter. Initial tests indicate that a time resolution of under 200 psec has been achieved in the cosmic ray test stand. Testing of the remaining counters is in progress. Counting rates due to radioactivity from the EC calorimeters have also been measured and the rates were low (<100 Hz) for expected discriminator thresholds.

A decision was made to use the CDF CAFE cards to measure the charge and time signals on the Luminosity Monitor readout electronics. The CAFE cards form the heart of the CDF calorimeter readout electronics and have the same form factor as a 72-pin memory SIMM. They integrate, digitize, and calibrate (via lookup tables) a current source input. With small modifications, the Run 1 Level Ø time-to-charge circuit should be able to drive the CAFE cards making the time measurement. A prototype board is currently being designed that will allow testing of all aspects of the Luminosity Monitor readout board design.

The multichip module is in the layout stage at the vendor. The design was modified to accommodate the latest SIFT changes and to correct some errors. The VLPC cassette test stand has become operational and is being used to look at noise in the four-cassette cryostat. The full complement of electrical engineers is now available, and the group is working on the next-generation prototype front-end boards for a test after the multichip modules are delivered. Detailed designs for about 50% of the functional blocks of the front-end boards have been completed. Great progress has been made on the design details for the final version of the TDR, including a concentrator crate design and the data contents and format into the Level 2 preprocessor.

DØ Note 3493 was prepared on Forward Preshower triggering. Threshholds for electron and photon high p_T triggers were established from Monte-Carlo and it was found that an isolation cut was not useful. The time required to implement the algorithm in Level 1 FPGAs is within the time budget.

A request was made that the central preshower clusters transferred from the fiber tracker Level 1 trigger carry a bit indicating the presence of a fiber tracker Level 1 track using that cluster. This functionality is required to permit triggering on central photons at Level 2.

Draft settings of the SIFT input charge division capacitors were established. A solution has been found that enables trigger threshholds in the range of 5 to 10 mips for high E_T electrons and photons and lower threshholds of 2 to 5 mips for the central preshower and forward preshower (downstream) and 0.3 mips for the forward preshower (upstream). The ability of the SIFT card to achieve the desired divisions must still be checked.

The desire to achieve an absolute calibration of the energy deposits in the preshowers leads to a proposal that permits settings with single photoelectron sensitivity during special runs. Modification of the SVX full-scale gain for these runs will help, but for the lower gain showering layers, it may be necessary to modify the charge division factors via downloads. The viability and desirability of this calibration is being studied.

No engineering work has started on the Level 1 calorimeter trigger. In this quarter the primary tasks have been re-examined and are listed below.

• Receipt of the new faster analog Trigger pick-off signals from the Run II BLS cards. This includes understanding their calibration.
• Buffering of event data and readout to Level 3.
• Buffering and supplying calorimeter data to the Level 2 calorimeter preprocessor.
• Generation of the "virtual reference sets" for making the concatenated "jet" lists
• Generation of "quadrant" signals for electrons and jets
• Construction of terms that come from the Level 1 calorimeter trigger compatible with the requirements for And-Or Input Term reception by the Run II Level 1 framework.
• Design and construction of a new control connection between the Level 1 calorimeter trigger and the new Run II Trigger Control Computer (TCC). Porting or rewriting the Level 1 calorimeter trigger control software and exerciser diagnostics software to run on the new Run II TCC. As the design and construction of the Run II framework is completed during this next quarter and that project moves into an installation and commissioning phase, a detailed description of the proposed work on the Level 1 Calorimeter Trigger will be prepared.

The progress achieved this quarter for all muon trigger cards is summarized in the following table:

At Arizona, the final MTT prototype was produced and is being assembled, the design of the first prototype MTCxx was completed and sent for layout, design work on the final prototype MTCM continued, and two of the three MTFBs were designed and the first of these was sent for layout. Testing of the final SLDBs also continued, with error-free signals transmitted 125' with no splitting. With the present splitters, the maximum error-free length is about 75' so a repeater chip will be placed in front of the splitter chips to increase the error-free cable length. At Boston, the first prototype MCCM layout is nearly complete and testing of the MCEN and MCPB continued.

Lastly, a plan was developed to port the Level 1 muon trigger simulator to C++. Initially, the bulk of the existing simulator will remain in Fortran and C++ routines will be written to unpack the needed data and to pack the answer in a manner compatible with the DØ simulator.

Engineering effort is currently directed towards a prototype 2-channel Cypress HotLink transmitter/receiver design. This "pre"-prototype is intended to accomplish the following:

1. learn how to use the Cypress board
2. learn about design considerations for multi-channel Cypress boards
3. be able to measure bit error rates
4. learn how cable length is related to bit error rates and be able to choose the least expensive cable/connector combination for the final design.

The transmitter component of this 2-board test setup is designed, laid out, and produced, and it is now being stuffed. The receiver component is designed, laid out, but not yet produced. Studies are underway of how to optimize the receiver test prototype development with the full MBT prototype. The above tests should be completed in November, after which full-scale prototype design will get underway. Much of the full-scale design will be similar to the 2-channel Cypress prototype.

Significant progress has been made on the definition of the event-level signal protocol on MBus between the MBT's and the Alphas for transferring an event. A technical design report for the MBT is in progress, and the portions covering this protocol and the Broadcast Output section of the MBT have been written.

The block diagram for the SLIC was revised and the first draft of a schematic is being prepared. A new digital signal processor from Texas Instruments has been announced that provides a 20% increase in speed and dedicated synchronous FIFO bus, ideal for use in the SLIC. Programming would be basically the same as the existing C6x DSP. Work continued on defining the I/O protocol for the Level 2 cables, and a draft document that includes the input state diagram is available on the Web. The SLIC technical design report has been revised to reflect recent design changes and the new protocol. The cable connections from the muon detector into the coaxial interface card (CIC) and from the CICs into the muon SLICs have been specified, and the muon group will be preparing cables into the CICs according to those specifications.

Three of the four cards of the demonstrator are fully operational, and G-link and Cypress have both demonstrated lock capture. The next phase of testing will begin as soon as minor problems with the Cypress transmitter card are resolved. The equipment will then be hooked up as a full FIC simulation. Various options for the final implementation were considered at a September workshop. Discussions are underway on whether to do the G-link receiving with a VTM card (which has implications, likely requiring a modified Magic Bus backplane) or Finnisar boards. A final decision will be reached soon on the size of the FIFOs and whether monitoring takes place via VME. Progress also was made at the workshop on a number of questions relating to the G-link and Cypress protocol and special symbols.

The Level 2 calorimeter group completed the technical design report that contains information on the I/O for the system, studies of bus loading and latency, queuing simulations, online control software and event loop, status of the algorithms including realistic timing simulations, and effects of vertexing on jets, electrons, and missing E_t. The logic for the event loop for multiple workers was completed, and work on the jet algorithm progressed. A draft of the design of the slow and fast monitoring system has been produced.

A test station was set up at the University of Illinois-Chicago that included a VME crate connected via a BIT3 interface to a PC, and communication with the crate via the BIT3 software was established. However, attempts to communicate with the crate using the Fermilab Fission package were unsuccessful and discussions with the Fermilab Computing Division continue in an attempt to resolve this problem. Several test programs have been written to test the BIT3 connection and more software has been written to test the Alpha processors. These programs have been exercised on the PC164 system at UIC. In collaboration with Michigan State, many pieces of the data movement software for the Administrator and Worker also have been developed.

A version of the forward muon segment-finding algorithm for the SLIC was completed, and table requirements for the central muon low-p_t segment algorithm were studied. Results of that study were used to guide the memory designed on the SLIC.

Level 2 triggers for the FPS and, to some degree, the CPS, have been simulated. Cluster sizes, occupancies, and trigger rejections from preshower and calorimeter matching have been studied. The preshower preprocessor algorithms for the FPS and CPS are expected to be similar, based on lookup tables for stereo matching in the respective detectors. The gains expected in Level 2 rejection from the use of the x,u,v layers in the CPS have been demonstrated for the CPS. Use of the spatial coincidence of the three layers gives a factor of two to three improvement, so transmission of the helical u,v layer information from the CPS front ends for Level 2 use is still desired.

Most of the data movement software design has been finalized and the code written. The remaining routines to be designed and written center on the low-level hardware interface. A simple emulator environment was written to allow software testing without the hardware, using shared memory and signals to simulate the busses. This has enabled testing of a simple administrator prototype that can currently communicate with a single worker. The Level 2 and Level 3 high-level configuration languages have merged to allow a single file to specify the trigger configuration. The syntax of the trigger bit scripts has been finalized to a large extent and a draft design for the Level 2 qualifiers exists. The language is now being documented to enable fine-tuning.

LINUX is now being considered for use in the runtime environment. Means of bypassing the kernel have been studied which may allow the runtime executable to run as a LINUX process without excessive overhead. These methods will now be tested to determine their suitability. The advantage of using LINUX will be greatly enhanced debugging facilities.

Work continued on the design and preparation of the technical design report for the Level 3 system. Plans also were developed for prototype systems to be installed at DØ. A test stand at the DØ silicon detector facility was used to readout silicon detectors. The test stand included a VBD and VRB controlled by a Windows NT node. The data was transmitted to a Level 3 analysis node through a MPM. The system operated at 630 Hz, a factor of ten greater than required for Run II. Great progress was made on the Level 3 operating software in preparation for the silicon test stand. The software operated very well.

With NT release procedures made public, remote installation is being shaken out. This is key to getting remote NT development of the Level 3 tools within the ScriptRunner framework. Work also continued on the Level 3 Parser (which parses the trigger programming that will be downloaded to ScriptRunner), implementing default parameter values, parameter range checking, and error reporting, and the Parser also is being updated to accommodate Level 2 needs.

Though it will continue to evolve, the format of tool and filter parameters has been established. This includes coordination with Level 2 to standardize formats as much as possible across trigger levels. A Level 2/Level 3 meeting was held during the recent Computing in High Energy Physics conference to discuss formats for tool results and tracing trigger objects. A demonstration graphical user interface for trigger list building is being developed that will be complemented by a text-driven executable that will run on any platform.

A major success was reaching the reconstruction milestone that calls for the production of raw data in crate format for at least one sub-detector (calorimeter). Monte-Carlo data packed in crate format is required for the development of all unpacking tools. A specification document was produced that described the functionality of the trigger simulation, and meetings were held about adapting existing Level 1 simulator software. This will involve collecting software from perhaps four or five contributors, replacing Zebra calls, and providing C++ wrappers. The first step will be checking the performance of the current software on UNIX platforms.

This quarter has seen significant advancement in Online System software products. Thanks to the contributions of the Computing Division, there is now a first version of the Client/Server communications package. Higher-level application development is now proceeding based upon this package.

A set of EPICS drivers and records now fully support 1553 bus devices. Work continues on the development of complete applications (including graphical user interfaces) to support specific devices. Other EPICS efforts have been in support of the SVX Sequencer download. The Rack Monitor Interface control code has been tested. The Controls group is also proceeding with the EPICS interface to the DØ Clock (accelerator synchronization and general timing) system.

With the successful implementation of 1553 support, the functionality of the legacy Token Ring-based front ends can now be reproduced. The plan is to replace those front ends with EPICS-based processors to make a uniform control system with no remaining legacy hardware or software. This greatly simplifies the development and maintenance efforts.

The legacy RDB database which supports the Controls system has now been exported into ORACLE, which is the Run 2 database system. This is with a general Computing Division installation of ORACLE -- a local installation of ORACLE on DØ Online nodes is about to begin.

The focus of the Online group is now centered on integration and commissioning of components. Effort is being aligned with early detector commissioning activities, including ICD, Calorimeter, and Central Muon tests. Specific applications with later general expandability are being developed in support of these efforts. Recently, the Online group has also had an infusion of manpower, with the addition of a new co-Head and a Computing Division Associate Scientist who will assume the leadership of the Event Monitoring sub-group.

The following table lists DoE (M1) and Director's (M2) milestones whose baseline dates fall before the end of the fourth quarter of FY98. (Milestones reached prior to the fourth quarter have been deleted from the list.). One DoE milestone was reached during this quarter. On Sept 30, 1998 the solenoid magnet testing program was completed with the successful operation of the magnet at full current followed by initial field mapping. This milestone was reached only a week later than its baseline date. Because of the lateness of this quarterly report, two Director's milestones that were actually met in FY99Q1 have also been included in the list of completed milestones.

This section presents a table summarizing the reported and scheduled (based on Jan 98 baseline) Fermilab technical effort during the quarter for each WBS Level 2 Subsystem. This includes reported effort from various engineering and technical teams and technical centers at Fermilab, but does not include physicist or project management effort. Units are in FTEs per quarter. Numbers under the "S" column headings denote Scheduled effort; numbers under the "R" headings denote Reported effort. CP - Computing Professional, DES - Designer/Drafter, EE - Electrical Engineer, ET - Electrical Tech, ME - Mechanical Engineer, MT - Mechanical Tech.

The Cost Report was not available at the time of submission due to the early arrival of the Project Business Manager's new baby.