FY98Q3
Apr-Jun 1998

Major accomplishments during this quarter include:

• the installation of all the Central Preshower modules onto the solenoid magnet, a Director's milestone that occurred on May 21, 1998;
• the insertion of the solenoid into the central calorimeter, a DOE milestone that occurred on June 26, 1998;
• the completion of all planned modifications to the central muon system proportional drift tubes

Areas of concern currently center on:

• vendor production rate and delivery of silicon detectors.
• vendor delivery of HDI flex circuits.
• excessive dark current in the forward muon tracking system mini-drift tube detectors.

These are discussed in more detail in the individual sub-project reports. Discussions with current vendors continue. Possible alternate vendors are being sought in some cases, while ways to mitigate potential schedule delays are being studied in order to maintain the current baseline date of April 11, 2000, when the detector is scheduled to be rolled in and hooked up.

Preparations continued on the control dewar vacuum system with the installation of the roughing and turbo pumps.

A 24'x10"x16"steel I-beam and three pedestal support structures were prepared for the installation of the solenoid into the central calorimeter. The installation scheme provides for the insertion of the I-beam plus solenoid into the central calorimeter hole with the solenoid near one end of the beam so that after the central pedestal is removed the solenoid can roll into its proper location. Mounting brackets were fabricated in anticipation of their being welded onto the central calorimeter vacuum vessel.

In preparation for installation, optical survey work was completed before installation of the pre-shower modules. The 24 central pre-shower modules were then installed around the solenoid and Pb converter. The installation beam was temporarily attached to the solenoid to test the installation procedure. Survey data were studied to understand where to place the solenoid with regard to the end calorimeters and the vacuum vessel of the central calorimeter. On June 25 the solenoid and its installation beam were placed on the installation pedestals and on Friday, June 26 the solenoid was rolled into its nominal position inside the central calorimeter.

Qualifying of hybrid vendors and ironing out production problems took place during April and May. Full ladder production began in June. This date was set by the availability of assembled HDI hybrid circuits. A vendor was found that could assemble hybrids with good yield at a reasonable cost. Work on first-pass hardware, software, and procedures for ladder testing and burn-in also was completed. Approximately 30 HDI hybrids were assembled and tested. Using these HDIs, 6 "right-handed" ladders were assembled and tested. Production of other ladder types is contingent on the delivery of HDI flex circuits by Litchfield Precision. These are behind schedule.

Designs for "F" disk support structures have been completed and these parts are now being ordered. Design of "H" disk assembly fixtures and supports is also nearing completion. There has also been progress on plans for detector installation and cabling. Assembly fixtures for 9-chip ladders were commissioned and prototype ladders were constructed. Three additional bulkhead pairs were received and measured. One "passive" bulkhead was returned for repairs. The final phase of the design of the overall cooling system is underway. A refined design for the half-cylinder support was examined and will be tested next quarter.

Two "old" style test stands are being used for ladder production testing. First articles of the final, sequencer-based test system became available at the end of June. The sequencer system will be used for a "full crate" test of the DØ and CDF readout electronics. It will then be incorporated into the burn-in electronics for use in production testing.

During this quarter work on the Lab 3 facility was essentially completed. The clean rooms are operational, the LK coordinate measuring machine has been installed (but not yet calibrated), and the HVAC systems are working. Procedures for the fabrication of carbon fiber support cylinders have been finalized, and preparations for fabricating a final set of short-length (24") prototypes are underway. The mandrel for cylinder number 3 has been returned to Fermilab after being ground to correct for out-of-roundness, and it has been sent to IB4 for quality control checks. Ribbon R&D also continues. A mold set for cylinder 3 is complete, and prototype tests of ribbon mounting will be done later this summer with the 12" prototype mold set and the prototype 12" support cylinder. VLPC testing continues at Boeing where some small bugs continue to be found in their operational parameters, but the Boeing group is approaching production-level testing.

The major pieces of the support frame -- aluminum ribs, support rings, module boxes, and outer rings -- have been rough-cut to size, and the detailed machining of these elements has begun at Stony Brook. Initial lengths of all of the wavelength-shifting fibers for the detector were determined, and they are currently being rough-cut, polished, and sputtered with aluminum on one end at Fermilab. Six stations have been established at Brookhaven to facilitate module construction and curing, testing, box construction and alignment, support structure assembly, overall detector assembly and alignment, layering, and the mock-up of the installation scheme. Two of these stations contain machined, 6-foot diameter domes that were cut to a 100-inch radius, mocking the shape of the EC cryostat heads to which the FPS will be mounted. They will be used extensively during detector assembly. Coupling mounts for the 64-channel phototubes have been designed and machined. The PC-based test station is continuing to develop and digitized readout has begun. Routing of the clear fiber bundles has been established, including the run through the cable winder, the interface to the intercryostat detector (ICD), a first mapping to the VLPCs, and the run over the ICD and through the outer radius of the cryostat. The scheme is being finalized in preparation for bundling the clear waveguides at Notre Dame. The die for scintillator extrusion has been machined (at an outside vendor) and a test run using it was made at a new vendor in New Jersey. A number of complications at the vendor end have delayed the final extrusion since the order was placed in early March of this year. Lastly, Monte Carlo, trigger, and reconstruction work continued.

The VRB board bid was closed and the bids are being evaluated. Testing of the SVX sequencer card prototype was completed and the production order was released for bid. Testing of the SIFT chip began this quarter and about two-thirds of the chip was fully functional. However, a layout error was discovered in the remaining part. This is being patched by a focused ion beam technique at Acurel Corp. The multichip module layout was completed by the vendor and is under review at Fermilab. The design of the controller card for the VRB module was completed and layout is under way. A stereo board prototype for the VLPC readout is now working and will be installed on the test cryostat for final testing. The final design of the front-end cards for the VLPC is underway and layout is expected to start at the end of the fourth quarter of FY98.

While collecting data with the test jigs, it was observed that some FETs started to fall off or stop making contact on the samples. Since the preamp design has two FETs in parallel, it continues to work with only one, but the noise and impedance increase. The changes are subtle (unless the FET falls off!), so an impedance-matching circuit was added to the test jig to detect impedance changes due to the loss of an FET. Data using the impedance-matching network are now being collected for all species, and the design should be approved very soon. The test procedure for the vendor has been written and translated into Korean, and the jig and procedure should be shipped in July.

The final preamplifier hybrid designs have been released to the vendor. The problem with the loss of FETs on hybrids was studied and understood. The conclusions were that the fault is not due to parts or the assembly process. Better packaging and handling was recommended by the vendor and will be implemented. In addition, the final devices will have a conformal coating that will secure them. The coating was not present in the tested samples. The pre-production 5,000-piece order is under construction, and all parts are in hand.

The addition of keying pins to the hybrid sockets on the motherboard has been discussed with the motherboard assembly vendor, and the cost is understood. All parts for the pre-production run of 110 preamplifier motherboards are in hand and the construction is beginning.

All (24) of the switching power supply units from the vendor (Vicor) have been delivered, and fine-tuning of the final design and the mechanical housing are nearing completion. Most of the electronic parts have been ordered.

Efforts to understand the SCA chip yield problem continue. The chip design files were obtained, allowing the production of a working Spice simulation model of the device. A probe card was built to test the uncut wafers in an attempt to understand the failure mode that has been localized to the output amplifier stage. Also, a few packaged chips (both working ones and ones which fail) have been shipped to a company that specializes in diagnosing chip failure modes. There is still no understanding of why the device is failing. The symptoms appear to be output offsets that are higher than specified and an associated non-linearity in response. It may be possible to use these higher offset devices once the impact on performance (e.g. linearity) can be characterized, but it would significantly complicate the calibration process. Discussions with the chip vendor (Orbit) continue. Currently, these delays are not expected to delay the project significantly. The SCA burn-in board is being routed and about one person-week of work is left before boards fabrication can begin. In the meantime, testing of packaged SCA chips continues, but no new devices will be packaged until the problem is understood.

Most shaper hybrid work has been put on hold until the new motherboard design is built and tested. Three tentative decisions have been made: (1) the shaper hybrids will be split into two parts, one doing the shaping and trigger pickoff, the other producing the dual range outputs; (2) the shaper will be a simple RC differentiation circuit and not the more complex Sallen-Key design in order to keep a unipolar signal with low frequency rejection obtained using the baseline subtraction method of Run 1; (3) the trigger shaping will be optimized for the 132 nsec bunch spacing. The "dual-shaping" solution has been tabled, since it would require a complete re-learning of the channel-to-channel (and overall) gain of the trigger system, requiring at least one extra iteration on new pickoff resistors.

The first fully functional BLS motherboard has been assembled, and testing has started on the analog part. Testing of the digital part, including the analog storage awaits the completion and testing of the first prototype timing and control module.

Work on the schematic for the replacement BLS backplane began.

Additional functionality is being added to the prototype testing board for the FPGAs needed in the Timing and Control System. This added functionality allows the board to also function as a test controller for the first BLS motherboard, including readout that is fully synchronized with that from Run 1. It will also be capable of connection to the SCL.

Design work on the pulser system hardware continued. The present plans call for a prototype pulser to be available at Fermilab for preamp testing in the fall. Initial survey of the online calibration software project has been completed. The calibration software project has been divided into three smaller projects: (1) communicate with the hardware and download parameters to begin the run; (2) accumulate data from the detector and calculate the calibration constants; (3) at end of the run, compare the data obtained with the reference data in the database and put the new entry into the database. Work on the code responsible for collecting data and calculating calibration constants is in progress. The Paris group is interested in participating in this project and it will be finalized in the month of July. A preliminary version of the software is planned to be ready in the fall to be tested at the 5000-channel test stand at DØ. A full-scale version is required to be ready for testing by the beginning of January 1999.

Two scintillator-box prototypes were manufactured by different vendors, and one was selected as significantly superior. Discussions between the ICD and forward preshower detector groups on the interface region between the two detectors centered on mechanical support and cable routing. A solution was found that allows the FPS cables to exit without obstruction by the ICD and also allows for removal of ICD boxes, if necessary. A preliminary test with a scintillator tile and a Mitsubishi fiber cable showed a significant (factor of two) loss of light signal in the cable. Second prototype cables were manufactured by Mitsubishi using Bicron fibers, and yield tests were started on a half-inch tile with two wavelength-shifting fibers per channel using the sum/difference of the ADC distributions from phototubes at both ends of the fibers. Fibers polished at Fermilab and the University of Texas-Arlington were compared, and promising results were obtained with the new fiber polisher at UTA. Drawer fabrication setup was started with the goal of using a CNC machine to produce the multiple components. The electronics motherboard design was developed and a prototype was fabricated. Lastly, components of the LED calibration system were manufactured, including the scintillator block and diffuser, and the mounting unit for the fiber backplane.

108 additional counters were produced this quarter at Northern Illinois University, for a total of 178, and 76 were tested for a total of 145. The Institute for Theoretical and Experimental Physics in Moscow also began counter production, completing 115 and preparing to ship 50 of them. Design work on the counter mounting system was completed, and drawings were produced, checked, and approved. Construction of the 12 high-voltage fanouts that distribute high voltage to the A-phi and Cosmic Cap/Bottom counters also was completed.

All planned PDT modifications have been completed. All modified PDTs have been leak-checked and high-voltage tested, and small repairs of loose wires, etc. are in progress. New rails for installation and support of the bottom, inner layer PDTs were designed and requisitioned. Indiana University continues to assemble and install the high voltage service cards and jumper delay boards. Approximately 2400 (1200) are required, about 25% of each have been built and installed, and all 22 modified PDTs now have new service cards and jumper boards. Testing of prototype readout electronics also continued. Data were collected with a 3-deck PDT using the new motherboard, control board, and muon readout card, and data collection using a 4-deck PDT is in progress. A preliminary plan for the configuration of the Low Voltage Power Supplies (LVPS) was developed. Separate +5V and -5V supplies for both the digital and analog electronics will be used and take advantage of the 5V supplies in hand

Engineering of pixel octant frames and counter supports continued. Studies of frame deformation for several different designs were done, taking into account gravitational and magnetic forces. The baseline design is now an aluminum frame sandwiched by aluminum sheets. Materials have been ordered and a prototype will be constructed soon. Preliminary designs of the pixel layout for the intermediate (B) and outer (C) layers were completed and engineering of the pixel support brackets continued. Two designs were developed and manufacturing costs from industry and university shops are being investigated. Studies of the magnetic forces acting on the scintillation counter phototube shields were performed which demonstrated that at least in some areas of the inner layer, magnetic forces are large and comparable to gravity. Calculations of the magnitude of the force are in progress.

Cutting of the plastic for the inner (A) layer pixel counters was started at the Institute for High Energy Physics (IHEP) in Russia. 1500 pieces were rough-cut and are ready for a final polish before counter assembly. Clean rooms for counter assembly were set up and test stands for the finished counters were developed. All wavelength-shifting (WLS) bars have been produced by Dzerzhinsk and delivered to IHEP, and a production line at IHEP to cut, polish, and bend the WLS is operating. All magnetic shields and bases have been built and tested at IHEP and 2000 of them have been delivered to Fermilab and tested. The failure rate after transportation was less than 1%. Calibration system parts to be mounted on the counters were made and tested. Long-term (> 1 year) aging studies of phototubes and other parts of pixel counters continued, and no problems have been found so far.

All materials for counter assembly at IHEP, including parts for the calibration system, have been delivered to Fermilab. Originally, these parts and the remaining scintillator were to be shipped to IHEP in May 1998, but problems with Russian customs delayed the shipment. A new set of papers for duty-free entry was signed that should allow the container to be shipped in the next month or two.

A test setup for pixel counters is being developed at Fermilab to be used before counters are installed into octants. All major test steps were studied and optimized.

Finally, a review of the Forward Trigger technical design report was held in May and the design obtained the strong support of the DØ Collaboration.

Minidrift tube (MDT) production at Dubna continued. Production materials for the inner (A) layer MDTs, including endcaps, PVC envelopes, and aluminum extrusions, are available. After the MDTs for the first octant were built, the production line was halted because the tubes drew a large dark current. The problem, verified by microscopic examination, was defective anode wire. Discussions with the wire supplier pointed to a problem with their manufacturing process and they subsequently delivered new wire of satisfactory quality. However, production MDTs still have large dark currents, and this problem is being studied further. The gas leaks of the MDTs delivered to Fermilab were higher than specified and the process of welding the endcaps to the PVC envelope is being studied in order to improve it. Both the dark current and gas leak problems have slowed the production line but there is still little risk to the schedule because of the high MDT production rate that can be achieved once these problems are understood and solved. Work continued on developing tests at Fermilab for MDT's arriving from Dubna. The vacuum leak test was dramatically improved and other tests, such as the high voltage check, are also being optimized.

Engineering work continued on the MDT octant frames and alignment blades. One prototype frame was built by welding, but it did not meet the strict flatness specification so a second frame is being built using better welding techniques. Other octant frame designs are also being considered (for example, ones built around a very flat tooling plate or honeycomb structure). For the first prototype octant, the alignment blades will be made of aluminum. A design for a plastic alignment blade has also been developed and costs of manufacturing this commercially are being investigated.

University of Washington personnel continued to work on the design of the gas re-circulation system.

A review of the forward tracking technical design report was held in June. The report received the strong support of the Collaboration and useful suggestions for improvements were generated as well.

A summary of the status of various components of the muon electronics system that were worked on this quarter is given below:

A review was held to decide between the two designs for the MDT Amplifier/Discriminator boards. One used integrated circuits developed by Dubna/Minsk for both the amplifier and discriminator, while the other used discrete transistors for the amplifier stage. The amplifier IC met agreed-upon specifications and that design was chosen. Production of these ADBs should begin in the fall of 1998. Orders for all of the SFE production cards and DSP processors for front-end controllers were placed this quarter.

The muon electronics projects continue to need two full-time physicists for two years for software support of muon electronics and efforts are underway to identify personnel to fill these needs.

All of the main electronics boards for the Trigger Framework have been delivered except the Trigger Decision Module, which is currently at the assembly vendor. The technical design report for the Trigger Framework was submitted and reviewed in June, and the project is on schedule for installation at Fermilab during September of 1998. The only remaining construction projects for the Framework are three paddle boards that are part of the backplane wiring.

The main focus for the past few months has been testing of the production Framework circuit boards. Each card is tested in two stages. About half of the framework circuit boards have been processed through these tests. Most assembly problems discovered so far involve only one type of card. All of the other card types have been virtually free of assembly errors. While working with the circuit boards in this testing program, a power supply sequencing problem also was discovered and a modification was made to correct it.

The Luminosity Monitor scintillator was procured from Bicron and cut and polished by the Fermilab plastics group, the fine-mesh phototubes and base assemblies were procured from Hamamatsu and tested at Brown University, and assembly of the counters began. Work on the luminosity monitor electronics focused on the development of the FPGAs for the TDC boards. Synthesis and simulation software was procured that will allow the design of the FPGAs. The multiple interaction and the Level 1/Level 2/Readout buffering algorithms have been written and studied using the simulator.

Assembly of the Luminosity Monitor calibration/monitoring system began with the procurement of a monitoring computer, a fiber-optic link between the computer and the VME crate, and a VME digital delay board. The development of software that will be used to test the electronics locally and serve as a framework for the calibration/monitoring software to be used at DØ also started.

Two new electrical engineers were identified for the project. Both are transfers from other Fermilab divisions. The first will transfer to the project on 7/6/98. The second has accepted an offer, but no firm transfer data has been set. Two new physicists also are working on the project and each has committed to stay for at least a year.

Quite a bit of work has been done to organize the computer-aided engineering and documentation tools for the project, and work has begun to transfer the information from the technical design report into engineering designs.

Current effort has been directed toward the development of a block diagram that describes how the Run II Calorimeter Trigger readout will work, and to understand how to separate individual beam crossings in the Calorimeter trigger pick-off signals. The detailed design work for the modifications to the Level 1 Calorimeter Trigger to allow it to readout in the Run II DAQ will begin when the Trigger Framework is completed.

The progress achieved this quarter for all muon trigger cards is summarized in the following table:

The design and layout of the final prototype MTT card was completed, testing of the first prototype MTCM card was completed, testing of the first prototype MCEN and MTPB is in progress, and design work continued on the MTCxx card, the MTFB board, and the MCCM cards. A design review for the MCCM card will be held in mid-July, completing the series of internal reviews for all prototype muon trigger cards. Eighty pieces each of SLDB transmitter and receiver boards were delivered and tested, and are available for other systems to use, and a second version of the SLDB adapter card for testing with the Fermilab XBERT hardware was designed.

Workshops during the quarter helped to define the hardware design of components. A proposal for 965K$ of funding for Level 2 was submitted to the National Science Foundation. The hardware design team is now in place and the design has stabilized. First layouts of rack space were produced and first components were ordered. Planning began for software to test the prototypes of several hardware components that are expected during the next quarter.

An April workshop focussed on the design decisions for the Level 2 components, particularly the Fiber Input Converter (FIC), and most such decisions have been made. A follow-up meeting in May and subsequent discussions have largely frozen the input specifications of the Magic Bus Transceiver (MBT) and the Second-Level Input Computer (SLIC), and greatly simplified the definition of the Serial Command Link Fanout (SFO).

The design of the prototype Alpha processor was frozen and efforts turned to manufacture of the prototype, now expected in August instead of June.

The I/O section of the MBT card has been designed and is now being laid out, and some auxiliary cards for testing are being built. In addition, work has begun to understand how to build the serial command link (SCL) functionality onto the board. The MBT technical design report is being prepared.

The function of the SLIC was defined during a workshop in April and a block diagram resulted. The SFO was redefined from a formatter/fanout to an analog fanout which echoes an extra output from Level 1 SCL information added to the MBT specification. Work in May and June focussed on the input signals from the muon front ends. Nevis Laboratory is testing cables and will design a coaxial interface card (CIC) to re-drive and translate the muon signals to shielded twisted-pair for input to the SLIC. Rack space and cabling to a CIC crate is being worked out with the muon group.

Work began on a prototype FIC, composed of 4 VME 6U cards. The first card is being tested and the other three cards are being fabricated. When the four cards are working, it will be possible to build a simple FIC by connecting two cards with a ribbon cable.

The Level 2 calorimeter group completed specification of the logic for the multiple-worker event loop, finalized the bus loading/latency and queuing simulation studies, completed a study of vertexing effects at Level 2 for calorimeter objects, and finalized the jet, electron, and missing-E_T algorithm timing tests on the PC164 system at Universtiy of Illinois-Chicago. The jet algorithm was studied and an estimate of its efficiency for different seeds and minimum E_T thresholds was determined. The design of an emulation environment for developing data movement software and the first round of processor memory layout has also been completed. Many decisions have been made for the Test Stand in both hardware and software. A Bit3 interface will be used to communicate with the VME crate from a PC and the Fision package has been adopted as the low-level communication software. Several testing programs to debug the Alpha processors also were developed. Finally, a first draft of the Level 2 calorimeter technical design report was completed.

Two new physicists have begun work on algorithms for the central and forward muon identification. The processing tasks for both regions have been identified to the level of dividing tasks between the SLIC and the preprocessor alpha. An unoptimized forward muon algorithm for both low-p_t and high-p_t muons has been written.

A first draft of the CFT Preprocessor technical design report was written. Work on timing studies for the ALPHA processor in the CFT preprocessor crate also began with studies of simulation results for the occupancy estimates.

Timing comparisons between a C and a C++ scriptrunner have been completed. Using real triggers from Run I Level 2 data, it was determined that the C++ scriptrunner was, on average, 10% faster that the equivalent C program. This has lead to the adoption of C++ as the programming language for the Level 2 global and pre-processors.

Design of the data movement code has progressed significantly. A draft design of the administrator alpha node software was produced and is being checked and modified. This design already has led to changes in the FIFO code to make it interrupt-safe, and the interrupt and exception handlers have been adapted to the new C++ environment. A first version of the low-level trigger configuration language has been written and a parser has been tested. This converts the ASCII configuration file into an Alpha byte-ordered binary file for download to the cards. This scheme removes the need for a complex parser running on the Alpha boards and relies, instead, on a high-level parser to thoroughly check the file beforehand. Preliminary tests were performed using the Linux operating system on the PC164 board. These are aimed at producing a user-friendly diagnostic environment. So far these have shown that Linux can be installed easily on the standard PC164 board and that direct physical memory access is possible, which allows use of the same source code to access the hardware.

An upgraded VME readout buffer board (VBD) passed long-term operating tests, reading several VRBs at high speed without errors. The study of a prototype upgraded multiport memory board (MPM) continued, as well as design work related to the VME readout controller (VRC) and the other components that form the overall Level-3 data acquisition system. Operation of the test stand at Brown University included transfers into multiple channels of MPMs. The software package that handles multiple interrupts was rewritten to increase its efficiency, and the code was tested successfully. Related work involved testing the solution for providing the Level 3 filter package access to the event data blocks after they have been received via the MPMs. The Level 3 filter program will be tightly linked to the event data using a mechanism involving shared memory. After developing this capability in a stand-alone form, it is now close to being integrated into the overall framework.

Having achieved the March milestone of having a Level 3 node installed at DØ and connected to the data paths, applications and users were actively sought for the Level 3/DAQ. The silicon group responded to this solicitation, and a Level 3/DAQ system will be provided for the high speed, full crate test of silicon electronics this summer.

During June, several students at Brown joined the Level 3 effort, made great strides in mastering the code environment, and have already made serious contributions to the development of the first versions of a visual monitoring utility and a package for inspection of the raw data.

This quarter saw most of the online software development directed toward making progress in infrastructure components. A key piece, the Client / Server messaging system which underlies most Host applications, benefited from an infusion of effort from the Computing Division. Substantial design and coding progress was made, with a working version expected by late summer. Infrastructure elements of the Controls System were also worked on. With help from the Beams Division Controls Group, a driver for the 1553 field bus was developed for the VXWORKS operating system. This will lead into complete EPICS support for 1553-based devices, which include numerous DØ power supplies and rack monitoring components. A prototype data logger was developed and used in conjunction with Level 3 tests, design work on the calibration system continued, and the Online Group continued to support the Silicon Facility test stands, making use of the 'Control Path DAQ' system provided within DART.

The following table lists Level 1-3 milestones whose baseline dates fall before the end of the third quarter of FY98. (Milestones met prior to the third quarter have been deleted from the list.)

One Director's milestone and two Project Manager's milestones were met during this quarter. On May 21, 1998 the Central Preshower Detector installation on the solenoid was completed (a Director's milestone). Although about two months later than the baseline date, this milestone is far from the critical path. On April 10, 1998 readiness for the first VLPC cassette test was achieved, and on June 26, 1998 VLPC production was completed.

Three Director's milestones with baseline dates in the third quarter were not met. Two relate to the completion of 10% of the detectors for the forward muon tracking and trigger systems, and the third concerns the start of production for the forward preshower detector. Of the unmet Project Manager's milestones, three relate to delays in the completion of technical design reports, three relate to completion of pre-production or prototype testing, and four relate to the start of production for various systems. A comprehensive reevaluation of the schedule is underway to better understand the impact of the production delays and possible ways to mitigate the schedule slippages that have occurred so that the mid-April, 2000 date for having the detector rolled into the collision hall can still be achieved.

This section of the quarterly report presents a table summarizing the reported and scheduled (based on Jan 98 baseline) technical effort of Fermilab manpower during the quarter for each WBS Level 2 Subsystem. This includes reported effort from various engineering and technical teams and technical centers at Fermilab, but does not include physicist or project management effort. Units are in FTEs per quarter. Numbers under the "S" column headings denote scheduled effort; numbers under the "R" headings denote reported effort. CP - Computing Professional, DES - Designer/Drafter, EE - Electrical Engineer, ET - Electrical Tech, ME - Mechanical Engineer, MT - Mechanical Tech.

The third quarter of fiscal year 1998 closed with obligations for the DØ Upgrade Project totaling $4,440K on equipment M&S funds and $137K on Solenoid AIP Plant funds. As shown in the following chart and table, obligations fell short of planned equipment M&S spending by $2,126K. Complications with vendors continued to cause the postponement of a few large procurements, but these are expected to be resolved during the fourth quarter. Reviews with sub-project managers of FY98 progress and planned obligations lead to the expectation that approximately 80% of the Upgrade project's $10,500K FY98 equipment budget will actually be allocated during this fiscal year.

During the third quarter, Cost Estimate change requests were submitted to and approved by the Project Managers, resulting in some changes to the baseline cost estimate. None of these changes were at a level that required approval by the Fermilab Directorate. The Estimate-to-Complete (ETC) the Upgrade is currently $14.943K. In addition, the overall contingency performance shows a rate of contingency usage of only 25%. In other words, based on the completion percentage of each sub-project at the end of the third quarter, DØ has saved 75% of the contingency estimated on items already purchased.

The Project currently has commitments with universities and other institutions in the DØ Collaboration, via active Memoranda of Understanding (MoU), that total $5,907K. These funds constitute an obligation on the part of the DØ Upgrade Project and are regularly costed each month through invoices that are received as the work is completed. A list of the collaborating universities and other institutions is shown in the following table, as well as a more detailed breakdown of the commitments and costs. In addition, three institutions have purchased equipment for the Upgrade with their own funds: the Tata Institute for Nuclear Research, Bombay, India ($300.0K), the Institute for High Energy Physics, Protvino, Russia ($259.6K), and the Institute of Nuclear Physics of Moscow State University ($35.0K). Recently, the Project also received an MoU commitment from Michigan State University to purchase equipment with funds granted by the National Science Foundation (NSF) and matching funds from the University ($225K).