FY98Q2
Jan-Mar 1998

This report describes technical, cost, and schedule progress for the DØ Upgrade Project during the second quarter of FY98. Highlights during the past quarter include:

• A DOE review of the Upgrade Project in mid-January, after which the revised project schedule and cost estimate were accepted as the "current baselines", with a revised date on which the detector is rolled in and hooked up that is in mid-April of 2000;
• The submission of technical design reports for the Fiber Tracker, the Forward Preshower Detector, and the Level 2 global trigger processor.

Project spending remained within the budget and contingency performance has been excellent. While several spending goals were met, obligations through the second quarter of FY98 remained below the level of planned equipment M&S spending. However, the project continues to make efforts to increase its obligation of funds to meet the FY98 plan. Further details can be found in the Cost Report.

Beginning with this report, a section is included that summarizes Fermilab technical effort for the quarter. This section compares actual and scheduled effort (in FTEs) for each WBS Level 2 subproject and resource category (mechanical engineers, mechanical technicians, designers, electrical engineers, and electrical technicians.)

The control dewar platform was installed on the cryobridge, the control dewar, associated vacuum piping, and a valve network were mounted nearby, and the pre-radiator lead (Pb) was installed on the outside of the solenoid to prepare for the installation of the pre-shower modules.

After a final safety review of the electrical power and quench protection system, approval was granted to power the electrical system up to the end of the buss-work just upstream of the control dewar. The safety interlocks, power supply, filter network, current reversing switch, dump switch and dump resistor, current transductor, ground fault detector and water-cooled bus were all tested. By placing small pulses on the instrumentation leads that are monitored to protect the superconducting bus and magnet, the quench protection and the system for handling magnet/electrical system faults also was tested. After an intensive two week interval of tests, the electrical system met all design specifications.

The field-mapping apparatus, its control and DAQ hardware and software continued to be modified in preparation for future field-mapping exercises. Hall probe data were taken in a non-uniform field to understand probe calibration in a large gradient field. Small NMR probes were obtained to evaluate their future use for monitoring the 2T field during running of the experiment.

Ninety ladders have been partially fabricated and assembled without the high-density-interconnect (HDI) circuits. The HDI procurement and assembly is pacing this effort. Initial efforts at using an outside vendor to assemble the circuits were unsatisfactory. Work is now proceeding in parallel with an additional vendor, and changes to the procedures employed by the first vendor have been suggested. The low yield (30-40%) and slow delivery of the HDI substrates also has been a disappointment, so other vendors with similar capabilities are being sought. Low-volume laser and burn-in test stands are operational. The final versions of these stations will use electronics that will be available this summer. Lastly, the DART/EPICs readout paths for these systems have been successfully implemented.

Fixture development for the double-sided barrel detectors has made good progress and the start of first-pass assemblies should begin when HDIs arrive in April. Barrel insertion fixtures are being tested with dummy ladders, two more beryllium bulkheads are expected in April, and Kansas State University is producing a full-scale model of an H-disk assembly. Despite ladder production delays, the goal of a large-scale system test this fall remains. The detector delivery situation has improved, and prospects are good for beginning H-disk and F-disk production on schedule.

After a long delay due to vendor availability for fire protection equipment installation, work on the Lab 3 clean room facility is moving forward once again. Lab 3 is expected to be ready the first week of June. The Coordinate Measuring Machine for Lab 3 has arrived at Fermilab and is being stored until the clean room is ready.

There have been some problems with cylinder fabrication using the higher modulus carbon fiber, and tests have been scheduled to look into this. Ribbon R&D focussed on the production of the first full-length curved mold. This mold has now been fabricated and assembled and is at Lab C for measurement and quality control studies.

Prototypes of the optical mixer box connector were received. Measurements of the mechanical precision of the parts show that all features are well under the design tolerances. Optical measurements yielded an average optical coupling efficiency of about 92%. This is lower than expected given the mechanical measurements, and the source of this discrepancy is being studies.

The VLPC test stand, built at Fermilab, has been shipped to Boeing North American. A group from Fermilab was at Boeing during March to setup and test the system. Boeing is now doing calibration studies of their cryosystems (they will use four) and should be ready to start production testing early next quarter. Processing of the first eight lots of VLPC devices (HISTE VI) is essentially complete. Cryo studies of the prototype 1024 channel VLPC cassette cryostat continued. Some design problems have been identified and modifications to the system will be done as soon as there is a break in the testing of the first prototype 1024-channel VLPC cassette. VLPC cassette testing continued with focus on electrical noise and cyro-lifetime cycle tests.

The Forward Preshower Technical Design Report, was submitted on January 30, 1998, and a formal review of the design by an internal DØ review committee was held on February 26. The committee was satisfied that the design was sound, and recommended that construction begin immediately. A few details continue to evolve, but the design is essentially complete, and tooling for construction has begun. Several viable techniques for fabricating the spherically-shaped elements for the detector support structure are also being studied, taking into consideration the tight spatial constraints, final material hardness, acheivable tolerances, attachment methods, tooling, and production methods.

Final drawings for the scintillator were completed and submitted for quotes to the vendor who will do the extrusion. Drawings and tooling for the final detector are being prepared at both Brookhaven and Stony Brook. These include spherically-shaped mandrels to be used as construction templates, jigging designs, and support structure elements. Testing of the fiber and scintillator response is also proceeding. Investigations of scintillator-to-fiber cross talk, effects of heating on the scintillator response, and variations of the response along the strip have been tested. Strength tests of the support frame have also progressed, including stress tests of rib-to-ring connections using epoxy, riveted sheets, or both, deflection measurements of the sheet metal during module fastening, and the rigidity of various means of fastening the frame together. Progress was made on the calibration system, which will consist of an array of blue LEDs that uses a machined plexiglass element to funnel the light to the various fibers within a connector. Trigger and Monte Carlo studies have also progressed. The full FPS geometry has been installed and tested in the DØ Monte Carlo program, and a full data sample has been generated of single particles overlaid on minimum bias events of varying multiplicity, dijet events, and W and Z bosons. This sample provides the input to make decisions on trigger and other readout hardware parameters, and first results from this sample were produced.

The VRB board was released for bid for production manufacturing, eight production J3 backplanes arrived and met specifications, the SVX sequencer card ( formerly called the "port card") prototype was built and testing was nearly completed, and production quantities of all three backplane types arrived and were acceptable. Algorithm and other testing continued with the trigger test board. A new version of the SIFT chip arrived at the end of March. This will be mounted on a board for chip testing, which should be completed by the end of the next quarter so that production can be finished by late summer. The multichip module preliminary layout was completed and the vendor is working on the final layout. Ten prototypes are expected during the next quarter using chips that were received recently. A stereo board prototype for the VLPC readout was completed and awaits physicist manpower for testing. The redesign of the cable that carries signals from the VLPC chips to the electronics boards on top of the cryostats also was completed.

Testing of the packaged switched capacitor arrays continued and chip yields continue to be a major concern. Significant yield problems have halted further packaging until the problems are better understood. Detailed studies by the packaging vendor seem to indicate that the problem is not at the packaging house. Photomicrographs of unpackaged die indicate that some of the low yields appear to be attributable to a mask misalignment, but on the majority of the others the source of the low yields is not yet known. The symptom appears to be higher-than-specified output offsets. It may be possible to use these higher offset devices once their impact on performance (e.g. linearity) can be characterized. Discussions with the chip vendor are ongoing. Also, attempts are being made to obtain the layout files from LBNL. At present these problems suggest about a two month delay in the completion of the calorimeter electronics subproject. An SCA burn-in board for large scale testing also has been designed and is ready for layout.

Most shaper hybrid work has been put on hold until the new motherboard design is built and tested. Three tentative decisions have been made: 1) shaper hybrids will be split into two, one doing the shaping and trigger pickoff, the second producing the dual range outputs; 2) the shaper will be a simple RC differentiation circuit in order to keep a unipolar signal. Low frequency rejection will be obtained using the baseline subtraction method of Run 1; 3) the trigger shaping will be optimized for the 132 nsec bunch spacing. The "dual shaping" solution has been tabled, since it would require a complete re-learning of the channel-to-channel (and overall) gain of the trigger system and require at least one iteration on new pickoff resistors.

Layout of the baseline subtractor (BLS) motherboard was finished. After verification and manual adjustment, the design will be ready for board fabrication. The field programmable gate array (FPGA) chip used on the board has been designed and simulated. It awaits testing on the real motherboard.

All of the signals to remotely control the new BLS design have been specified, both at the board and the crate level. This was needed to finish the motherboard layout and to allow work to begin on the replacement BLS backplane design. A prototype testing board for the FPGA is being designed that will allow full verification of FPGA operation, independent of the BLS system. It also will have a test cable connection to allow a single BLS motherboard to be driven. The first prototype will only handle level-1 trigger requests and can be run via the standard serial command link daughter board or from an external source.

The French groups have agreed to undertake the design and construction of the calorimeter pulser. Preliminary designs have been presented and are under discussion and review. These initial designs have already led to a small change in the preamp motherboard design. Some initial progress also was made in constructing the software calibration system for the calorimeter. Planning for the new C++ code began and other collaborators are being solicited to help in this effort . Initial code has been written for the Level 3 nodes that will perform calculations of pedestals and gains.

Production of the four iron blocks that are the principle component of the magnetic shielding for the ICD Photo Multiplier Tubes (PMT) has been completed. One of them will be available for the solenoid test scheduled to begin in the summer of 1998. The fiber backplane enclosures also have been fabricated. Cosmic ray testing of the Run I ICD boxes was completed and the results showed that nearly all of the Run I PMTs are functional, though a larger than expected drop in gain was seen on average. Run I ICD Box decommissioning has begun, removing salvageable electronics such as PMTs, temperature sensors, and high voltage feedthroughs. The PMT test stand is nearly complete, and will be used to measure individual tube characteristics and determine optimal operating voltages for each tube. Testing of commercial fiber cables showed high transmission but some minor polishing and epoxying problems that are expected to be resolved in the next prototype. A manufacturer has been identified for the aluminum boxes that will enclose the tile modules, and final prototypes are being manufactured. Plans for the fanout of low voltage, high voltage, and pulser signals are nearly complete, as is the design for the motherboard, which contains the photodetection electronics through the preamplification stage. Current activities are focussed on the start of tile module and electronics production.

Counter production continued at Northern Illinois University. A total of 70 counters have been produced and tested. Parts were received for the medium- and large-sized A-phi counters by the Institute for Theoretical and Experimental Physics in Moscow, and counter production has begun there. All 630 PMTs, bases, and shields for the A-phi counter system were received and tested at DØ. Design work on the counter mounting system is on hold because the engineering and design team has recently focused on the forward muon system. Monte-Carlo simulation showed that the rate reduction with the A-layer "donut" shielding is only a factor of 1.1 to 1.6. Thus it was decided to remove this shielding as part of the baseline design but plan to do additional studies during the collider run.

Twelve A-Layer PDTs have been modified, two of those have been tested thoroughly, and the others await installation of service cards and jumper boards. The six A-Layer side PDTs are partially through the refurbishing procedure. One of these PDTs has been fully populated with new pads. Removal of the remaining obsolete WAMUS electronics, service cards and gas system from the muon trusses began and is about 80% complete. Indiana University personnel continued to assemble the 2400 high-voltage service cards and 1200 jumper boards. The first 3% are finished and installed. Indiana also fabricated an alignment jig so that the Phase 2 survey of the WAMUS tooling balls, partially covered by the scintillation counters, can be performed. Testing of the prototype PDT front-end and readout electronics also continued. The plan for the HV distribution for the PDT's was completed, and counting of the modules needed for fanin/fanout of the cables that carry timing information was performed.

The engineering design of pixel counters and associated support frames was a major area of activity during this quarter. The A-layer layout and counter sizes were finalized. Drawings were prepared, checked, and sent to the Institute for High Energy Physics (IHEP) in Russia so that counter production could begin there. Stress analyses of the various counter support frames under consideration were carried out, taking into account both gravitational and magnetic forces. At IHEP, cutting of scintillator plastic began, jigs to bend the wavelength shifting (WLS) bars and assemble counters were built, and all the WLS bars were delivered. Thus, all materials needed to start full-scale counter production are in hand at IHEP. Counter tests to be performed at IHEP and Fermilab as part of the production process also are being finalized. Approximately 80% of the magnetic shields and bases (including 100% of the 48mm diameter shields) have been built and tested at IHEP and a total of 896 bases and shields have been delivered to Fermilab. Fast tests to re-check the PMT bases at Fermilab were developed and all 896 bases were checked. Less then 2% of the bases had to have minor repairs. Studies of the LED calibration system parts to be mounted on each counter also were performed. Variations of about +7% between different counters were observed due to the optical connectors, but this is within the specification. Long term (>1 year) aging studies of PMTs and other parts of the pixel counters continued. Lastly, all twelve high voltage fanouts were received from Prague, tested at Fermilab, and met specifications.

During this quarter, the major activities were the engineering design of the A-layer minidrift tubes (MDTs) and their production at Dubna. Final drawings for all A-layer MDTs were produced, checked, and sent to Dubna. Work on the support frame and octant assembly procedure was also carried out. At Dubna, large samples of aluminum and PVC extrusions were received and met specifications, so orders for the remaining material were placed. Plastic endcaps and wire supports also were produced and delivered, and large-scale production of MDTs began. The present rate is thirty 8-cell units per day.

All MDTs are thoroughly tested as part of the production procedure. Tests include checks on the wire tension, gas integrity, and high voltage stability. During testing of the production MDTs it was found that they drew unusually large currents. Further investigation showed that the vendor-supplied 50 micron gold-plated-tungsten wire was defective (not smooth). The supplier was contacted and agreed with this assessment. They are producing new wire and are aware that this is holding up MDT production. A total of 165 MDT tubes have been delivered to Fermilab. These tubes were made with the defective wire, but the wire was hand-polished to make the tubes operational. These tubes will be used to assemble a prototype octant. Testing procedures for tubes arriving from Dubna are being developed. Radiation aging studies of MDTs using the materials selected for large-scale production are underway at Dubna and no degradation of MDT performance has been observed up to an accumulated charge that is well beyond the expected Run II dose.Finally, the University of Washington group recently joined DØ and has begun work on the specifications and design for the MDT gas system.

A summary of the status for various components of the muon electronics system is listed below:

Both the front-end board and the control board were tested using a PDT and a prototype muon readout card. Data were collected and the results will be presented at an upcoming IEEE conference. The design and layout for the FEB tester board were completed, while prototype testing of the muon digitization card awaits completion of the readout controller. The design of a tester card for the muon digitization card is also in progress. Both solid state and discrete versions of the mini drift tube amplifier-discriminator board are being assembled. New solid state amplifiers were produced and the dies are being tested. Printed circuit boards exist and assembly is in progress for both versions of the board. About 50% (by cost) of the muon processor boards were ordered. Finally, this subproject continues to have sharp needs for software support, especially for scintillator and readout electronics.

All of the main electronics cards for the Framework have been received except for the Trigger Decision Module (TDM). The design of the TDM is finished and the raw boards are being manufactured commercially. All of the components for the module, including the Field Programmable Gate Arrays (FPGAs), are in hand so that TDM kits can be sent to the assembly vendor as soon as the raw boards are received. The only remaining construction is a few "paddle boards" which are used in several locations where cables merge together. All but one of the FPGA designs are finished for the principal signal path through the Framework. Most of the remaining FPGA work involves the designs for special functions. Development work on testing boards involves verifying that the cabling is correct along a string of cards. Currently most of the software work is in support of developing these tests. A much different strategy is being used for this type of testing compared to that used in Run I. Because the functionality of a card can be changed just by loading a different program into it, the functionality of all the cards in a chain can be simplified for this type of testing so that the test concentrates on the connectivity and does not require the full Framework simulator (along with trigger programming and history context) to predict the outcome of a given input test vector.

A new Memorandum of Understanding between Brown University and Fermilab has been executed that includes the Luminosity Monitor subsystem. Orders were placed for the scintillator and photomultipliers, and design work is in progress for the enclosures and fabrication fixtures. In addition, the conceptual design for the electronics has solidified. High quality cables will bring the signals to the moveable counting house, where the time and charge will be measured for each signal. FPGAs will be used to calculate the vertex position and multiple-interaction flag. As described in the previous quarter's progress report, a new method for identifying multiple interactions has been developed that is based on the difference in time between early- and late-arriving particles. Since the Level Ø analog electronics design will be used for Run II with only minor modifications, most of the Luminosity Monitor electronics effort is in designing the FPGAs. FPGA design software has been procured and this effort has begun.

Recruitment of two more physicists to work on the design of the tracking code began. A next version of the code that incorporates priority track indexing was started and is near completion. Much work was done on the design of the system beyond the front-end boards. A complete design for the CFT Level 1 trigger was made as well as a design for the delivery of track information to the CFT Level 2 and STT Level 2 preprocessors. Design work was also done on the trigger electronics for the forward and central preshower detectors. A preliminary design was made for a forward preshower Level 1 trigger and for getting the forward and central preshower information to a possible Level 2 preprocessor. The design of this front-end closely follows the CFT front-end design. The global Level 1 design calls for the same hardware as the CFT Level 1, and the transmission of data to a possible Level 2 preprocessor uses the same hardware as the CFT-to-Level 2 link.

The full simulation of the forward (and central) preshower detectors in UPGEANT has been completed and samples of single electrons, pions, photons, and di-jet events have been generated along with several overlapping minimum bias events. First results from these samples are now available and confirm the previous level of rejections achievable with the FPS in the single-particle samples. Variables studied include the thresholds in both upstream and downstream layers of the FPS and the size and thresholds of possible isolation window requirements in the downstream (showering) layer. First results suggest that the isolation requirement is not very useful, however the Level 1 requirement of a tower in the ECEM quadrant behind the FPS module has been investigated and was found to be useful. Studies with full di-jet events will begin shortly, as useful samples from the Monte-Carlo become available.

Recent work on the Level 1 Calorimeter Trigger involves understanding the best way to generate the Calorimeter pickoff signals and deliver them to the Trigger. The goal is a solution that will work at both the 396 and 132 nsec crossing rate. The current design involves a terminator network at the Trigger end of this link. These terminator networks are a component that needs to be replaced for Run II in order to achieve the proper energy calibration of the Level 1 Calorimeter Trigger.

The progress achieved this quarter for all muon trigger cards is summarized in the following table:

Prototype testing of the muon trigger tester card (version 1) was completed. MTT cards are now being used at Brown University and the University of Arizona to debug the centroid finder and crate manager cards, respectively. Testing of the crate manager prototype is progressing well. Design work continued on the muon trigger card, flavor boards, and centroid finder crate manager cards. A design review for the trigger card will be held at the end of April. Eighty pieces each of serial link transmitter and receiver boards were ordered which should serve as final prototypes. CD XBERT boards will be used for more extensive testing of the SLDBs. A set of these boards was assembled and testing is in progress. Adapter cards used for testing the SLDBs were fabricated. Work also continued on the technical design report.

The Level 2 calorimeter trigger group added a postdoc from the University of Illinois-Chicago. The group began studies of the multiple-worker event loop, extended simulations of the Level 2 Cal system, took delivery of a 500 MHz alpha PC164 test system and a 500 MHz alpha Digital UNIX workstation for Level 2 code development, studied the effect of vertex corrections at the Level 2 stage, continued development of the missing E_T and jet algorithms, and began work on a data movement emulation environment. Based on simulations, it was decided that the Level 2 cal system will likely have to operate in an asynchronous worker mode. The development of the missing E_T code and tests on the PC164 system have shown that the algorithm can be run at the baseline 10 kHz input rate. The timing tests also show the jet processing time to be well within the time budget.

A conceptual design for the muon preprocessor SLIC was reached using the TI C6x digital signal processor (DSP) as the primary processor. Preliminary discussions have begun with Saclay to explore the use of the FIC as the input stage for the SLIC. An algorithm for the central low-p_t muon finder has been written in C and assembly language and tested on the DSP simulator.

The University of Maryland hired a new post-doc who will work on the MBT card and will take the lead on the integration and commissioning of the CFT preprocessor crate. The main activity this quarter was trigger studies of CFT Level 1 track occupancies. This is needed in order to estimate I/O bandwidth and processing requirements for the CFT preprocessor crate.

Conceptual design work for the preshower Level 2 preprocessor continued. The plan is to treat both the Central and Forward Preshower detectors on a similar basis. To provide the triggers needed for Run II physics, the preshower Level 2 information should permit identification of both electrons and photons. This means that the CPS axial and helical strips should be available to the Level 2 preshower preprocessor, without the requirement of a matching CFT track. Discussions with the CFT group have concluded that this information can be provided and the plan is to implement this. A further argument for adding the helical strips derives from the expectation that eta-phi matching of preshower and calorimeter EM coordinates will provide most of the Level 2 rejection. If the helical CPS strips are available, there is also the possibility to obtain a reasonably precise z-coordinate at trigger time. Whether the full digitized outputs from the preshower trigger pickoff chips are needed, or only simple high/low threshold hit patterns, remains to be settled with the Monte-Carlo events now being generated. Estimates of the time required for executing sample Level 2 preprocessor algorithms seem to fit within guidelines.

Several key pieces of software have been developed for the Level 2 Alpha VME boards. There is now an exception and interrupt handler, and a means to identify the cause of interrupts has been found. Timing routines using the processor cycle counter (PCC) have also been written. Some higher level code has also been developed, including FIFO and List C++ classes as well as uniform and gaussian random number generators. An emulation environment for developing data movement software has been designed and is being written using shared memory and signals to communicate between UNIX processes. Prototypes for the Level 2 trigger script runner have been implemented in both C and C++ to allow speed comparisons. When dynamic memory allocation is restricted to initialization only, tests show no substantial difference in speed between the C and C++. More rigorous checks will be performed before a decision on implementation language. Finally the algorithm for looping over the 128 Level 1 trigger bits is being optimized. Comparison between the various trial methods has shown that there is little to no gain in speed when writing assembly instead of C/C++ so a decision was made to use the DEC C++ compiler for all Alpha C/C++ code. The C++ compiler produces faster code (with optimization turned off), has better error checking, and ensures easier integration with the offline (C++) software simulation.

Good progress was made in the Level-3 trigger/data acquisition system hardware and related software. The highlight of the quarter was the delivery to DØ of a dual processor NT system and its installation on the existing data pathways such that it received data from the moving counting house via the multiport memories, handled the data locally, and sent it to a separate, receiving node. This system is a stand-in for the eventual, later generation Level 3 node to be purchased close to the time of turn-on; but it will provide a very important test bed for those at DØ developing associated software for Level 3 filters as well as for checkout of Level 3/DAQ framework software developed at Brown University on a local small version of the DØ DAQ. As noted, the output function from the Level 3 node was tested as well (in an early form), but because of the limitations related to the support of online system the data was sent to a separate workstation rather than to the host. At Brown, excellent progress was made with the test framework, built upon software in an NT system that interacts with hardware in a VME crate to provide a source of data transferred via the standard DØ data paths. Considerable work also focussed on the software in the Level 3 node, which included integrating into the framework the ACE package that will provide for DØ code standard wrappers around low-level utilities, including various thread management functions. The package THREAD_UTIL was created to provide key routines for use throughout the online systems. THREAD_UTIL has been released on both NT and UNIX (the first such package to be released as cross-platform). Additionally, a very important and useful collaboration was begun with the Fermilab Computing Division for work on the data logger.

Activity during the second quarter of FY98 has been related to the establishment of the software development environment. The Digital UNIX host node now supports the Fermilab product library distribution using the new upsII mode. Products have been installed in support of development and operations needs. The RAID disk set containing the products is also exported to a Linux node and will be the home for Linux development. The UNIX host now supports the standard KAI C++ compiler and development environment, in addition to the native compilers. Software activity has continued on the core infrastructure components - an application and intertask communication framework, and the EPICS control system fundamentals. The application framework progress is behind schedule, but additional manpower has been supplied recently by the Fermilab Computing Division. Development efforts have centered on the support of needs in the Lab D Silicon Test Facility, with the achievement of EPICS control of a movable table device. Further EPICS work is now focused on defining a framework under which specific applications will be developed. The DART data acquisition system is in use at Lab D. This comprises the 'control data path' which is expected to be useful in the commissioning phase of Run II. Slight modifications of DART are in progress to extend the commissioning capabilities. Also, DART components continue to be evaluated for direct use in Run II data flow and monitoring applications. The Online System Technical Design Report is about 75% complete. There are no technical difficulties, only the effort needed to record the current active designs. In June, the TDR will be completed and reviewed.

This table shows Level 1, 2 and 3 milestones whose baseline dates occur before the end of the current reporting quarter (3/31/98). Note that the baseline dates refer to the "current baseline" i.e. those approved following the DOE review held in January, 1998, and the listed variances are relative to those baseline dates. The milestones are sorted in ascending order, according to their current baseline dates. Three level 3 milestones were met during this quarter - The Fiber Tracker and Forward Preshower technical design reports were submitted in January and February, respectively, and the Trigger Level 3 System Test was completed in March. Six other level 3 milestones, none on the critical path, were not met as scheduled during the quarter. Revised dates for those are indicated in the table.

This new section of the quarterly report presents a table summarizing the reported and scheduled technical effort of Fermilab manpower during the quarter for each WBS Level 2 Subsystem. This includes reported effort from various engineering and technical teams and technical centers at Fermilab, but does not include physicist or project management effort. Units are in FTEs per quarter. Numbers under the "S" column headings denote scheduled effort; numbers under the "R" headings denote reported effort. CP - Computing Professional, DES - Designer/Drafter, EE - Electrical Engineer, ET - Electrical Tech, ME - Mechanical Engineer, MT - Mechanical Tech.

The second quarter of fiscal year 1998 closed with obligations for the DØ Upgrade Project totaling $2,162.4K on equipment M&S funds and $77K on Solenoid AIP Plant funds. As shown in the plot on the following page, obligations fell short of planned equipment M&S spending by $1,924K. Delays in design plans and complications with vendors caused the postponement of a few large procurements into the third quarter. During the second quarter, each Sub-Project received an allocation of equipment funds that tied directly to the Project schedule. Sub-Project managers are asked regularly to justify schedules and obligation plans and are strongly encouraged to stick to the plan. The Project anticipates obligating all of its $10,500K budget allocation during the current fiscal year.

Beginning with the second quarter, calculations are now based upon the new baselined Cost Estimate approved during the January 1998 DoE Review. The Estimate to Complete (ETC) the Upgrade is currently $16.427K. In addition, the overall Contingency Performance shows a rate of contingency usage of only 18.9%. In other words, based on the completion percentage of each Sub-Project at the end of the second quarter, DØ has saved 81.1% of the contingency estimated on items already purchased.

The Project currently has commitments with universities and other institutions in the DØ Collaboration, via active Memoranda of Understanding (MoU), totaling $4,743K. These funds show an obligation on the part of the DØ Upgrade Project and are regularly costed each month via invoices received from the universities and other institutions as work is completed. A list of the universities and institutions involved, as well as a more detailed breakdown of the commitments and costs, is shown on the last page. In addition, three institutions have purchased equipment for the Upgrade with their own funds - the Tata Institute for Nuclear Research, Bombay, India ($300K), the Institute for High Energy Physics, Protvino, Russia ($260K), and the Institute of Nuclear Physics of Moscow State University ($35K).