The analog front end board. This board comes in two versions, the first with 8 MCM's is used for the CFT fibers, while the second with 12 MCM's is used for the preshower strips. Each of these boards contains the MCM with the SIFT and SVX chips. Further, these boards control the VLPC bias voltages and the cryogenic controls for each cassette.

The digital front end Mother board. This generic motherboard is used threw out the project. It has high I/O bandwidth and will accept any of several types of daughter boards. It also has a Transition Module located behind the back plane.

The Track finder Daughter board finds the CFT axial tracks, and CPS axial clusters, and sends this information to the L1 and L2 Triggers.

Project Engineers - Jamieson Olsen (hardware), Manuel Martin and Juan Lizarazo (firmware)

The collector board collects the inputs form multiple digital front end board and merges the data. This data is then sent to the broadcaster board, which sends the data on to the L1 and L2 hardware. There are few physical boards but each requires a different custom version of the firmware.

The digital transition board is located behind the backplane in the digital board crate. It receives through the backplane the output of the digital board and transmits it. Either each DTB has four independent lvds-channel-link outputs and two slaved outputs into which a G-link or an AMCC daughter card can be plugged.

The mixer box consists of 20 boards located in a single 6U VME 'type' crate. The signals at the detector are arranged into ribbons which contain fibers from the same detector layer. The signals must be re-arranged into trigger sectors which are r-phi wedges. The Electronic Mixer Box, MB, sorts the signals from their orientation in phi into the trigger arrangement. The MB must sort all the signals from the detector for each 132ns bunch crossing using the seven 53MHz clock ticks. Thus 1/7th of the data enters the MB each clock tick and some time later that same 1/7th of the data departs sorted. The sort is different for each of the seven clock ticks. And the total time in the MB, the latency, must be less then 7 clock ticks in order for the Track Trigger to meet its time budget for the L1MUON seed tracks. The total MB data rate is over 300Gbits per second.